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Sidense Company Description


Sidense IP Catalog

84 Hines Road, Suite 260
Ottawa Ontario K2K 3G3

Sidense's 1T-Fuse™ Logic NVM IP is based on a patented, one-time programmable (OTP) technology that provides the most cost-effective and reliable OTP solution in the industry. No additional mask layers or process steps are required and the IP is portable across many different technology nodes and foundries. The OTP can be programmed in the field, at wafer probe, or during production testing. Sidense memory products are targeted to standard-logic digital CMOS processes that are 180nm to 28nm and smaller and are available for all Top-Tier foundries and selected IDMs.

Additional features include field-programmable OTP and emulated multi-time programmable (eMTP) modes; a very small footprint using one transistor per bit; programming voltages supplied on-chip; very fast read-access times, greater than 10-year retention at 125°C and a 100% read cycle; conversion to mask ROM with a single diffusion mask and no process changes; JTAG and BIST support; extremely secure and almost impossible to reverse engineer (no charge storage); very reliable at high temperatures; and seamless integration to ASIC and COT.

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In the News

Sidense Exhibiting at TSMC Technology Symposiums
04/02/2013

Sidense 1T-OTP NVM Qualified for 150 Degrees C Automotive High-Reliability Requirements on TSMC's BCD Process
04/01/2013

Sidense Qualifies 1T-OTP Non-Volatile Memory for MagnaChip 180nm Mixed-Signal and HV CMOS Process
03/25/2013

More News

Testimonials

"The protection of media content is an important feature of our product line. We found that the technology represented by the Sidense 1T-OTP memory IP was the best available for implementing the level of security that we and our customers require."
Steve Musallam, Magnum Semiconductor

More Testimonials

Tech Talks

1T-OTP - The Ideal NVM Solution for the Growing Mobile Device Market
(05/07/2013)

One-Time-Programmable Memory for Power and High-Voltage Semiconductor Applications
(03/05/2013)

Using Cost-Effective and Secure Field-Programmable 1T-OTP to Emulate MTP
(12/27/2011)

More Tech Talks

White Papers

1T OTP Memory: Delivering Quality and Reliability
(11/05/2009)

Reduce Chip Power with Antifuse OTP Memory
(11/04/2009)

Sidense OTP Macros for Security Applications
(11/04/2009)

More White Papers

Contact Sidense

Do you have questions on the Sidense IP offerings listed here? Our IP Concierge service can contact Sidense and other IP vendors on your behalf and they will reply to you directly. You may also send a message to Sidense regarding their IP by clicking here.

Latest Sidense IP

IP Vendor IP Name Description
Sidense SiPROM_TSMC90LP25_2Kx32_1S4Y2_AG OTP/eMTP: 64 Kbit NVM in 90nm Standard Logic CMOS process
Sidense SiPROM_IBM65LPe25_4Kx16_1S8Y2_AF OTP/eMTP: 64 Kbit NVM in 65nm Standard Logic CMOS process
Sidense SiPROM_SMIC90LL33_2Kx32_1S4Y2_AG OTP/eMTP: 64 Kbit NVM in 90nm Standard Logic CMOS process
Sidense SiPROM_TSMC65LP33_1Kx16_1S2Y2_AF OTP/eMTP: 16 Kbit NVM in 65nm Standard Logic CMOS process
Sidense SiPROM_CHRT130G33_4Kx8_1S8Y2_AC OTP/eMTP: 32 Kbit NVM in 130nm Standard Logic CMOS process
Sidense SiPROM_CHRT65G25_1Kx8_1S2Y2_AF OTP/eMTP: 8 Kbit NVM in 65nm Standard Logic CMOS process
Sidense SiPROM_TSMC90G25_2Kx64_2S4Y2_AG OTP/eMTP: 128 Kbit NVM in 90nm Standard Logic CMOS process
Sidense SLP_TSMC180G33_512x8_CM8D_AE OTP/eMTP: Very low power 4 Kbit NVM in 180nm Standard Logic CMOS process
Sidense SiPROM_TSMC65GP25_4Kx8_1S8Y2_AF OTP/eMTP: 32 Kbit NVM in 65nm Standard Logic CMOS process
Sidense SiPROM_UMC65LL33_4Kx64_2S8Y2_AF OTP/eMTP: 256 Kbit NVM in 65nm Standard Logic CMOS process

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