Standard Chip Estimation Methodology

Udupi Harisharan
Sr. Hardware Engineer
DSS-COT, ISBU ASIC Engineering
Cisco Systems

ABSTRACT

Accurate chip estimation can significantly and positively impact overall packaged die cost and accelerate time from specification to product. For an architectural level estimate to correlate to final silicon, estimation models and algorithms must encapsulate a detailed understanding of cell libraries, I/O's, memories, other IP models, as well as the process and manufacturing technologies used for implementation. Cisco evaluated Chip Estimate Corp's InCyte system for its ability to quickly improve our estimation of chip area as well as for architectural trade-off analysis at the early stages in the design flow. This paper discusses the circuits and criteria Cisco used for the evaluation of the InCyte chip estimation system, the outcome of the evaluation, and the resulting recommendations.

1. EVALUATION OVERVIEW

Cisco undertook this evaluation in order to assess whether using the InCyte system would improve our chip estimate to silicon correlation, and if the system could improve the consistency of chip estimates in general. We define "chip estimation" as the estimation of chip die size, power, leakage, and cost at the architectural stage of the design flow. The architectural stage in the design flow may span early planning and viability assessment through to initial RTL design and implementation - all while architectural decisions continue to be assessed as a specification is finalized.

Another key consideration in our evaluation of the tool was the ability for the system to perform fast "what if?" analyses, enabling and facilitating our consideration and selection of the best IP, process technologies, and chip architecture options for a given chip project.

To conduct the evaluation, we identified two completed ASIC designs to be used to benchmark the InCyte system. We decided to compare InCyte estimation results with actual silicon as well as our previous estimation methods. The first would tell us how accurate the tool was with respect to silicon correlation and the second comparison would reveal how it differed - either better or worse -- from the methodology we already had in place.

Our stated goal was to see if InCyte could accurately estimate our silicon die size with 90% or better accuracy (within 10% of silicon).

Both ASIC designs used for the InCyte evaluation were fabricated in the TSMC 130nm LV (Low Voltage) process with 8 layers of metal.

The tape out specifications for the first completed circuit are listed below.

Bridge ASIC

5.7 million gates
11.9 MBits of total memory
3.6 MBits of 2P SRAM
6.7 MBits of 1P SRAM
1.6 MBits of register files

The second completed circuit had the following tape out specifications.

PORT ASIC

6.8 million gates
4.36 MBits of total memory
3.2 MBits of 1P SRAM
1.16 MBits of register files

Both the Bridge and PORT chips utilized Artisan (ARM Physical IP) LV Sage-X standard cells libraries, I/O pads from various third parties along with Virage Logic STAR memories.

2. SET UP FOR THE BENCHMARK

After selecting these designs for the benchmark, we input the chip specifications into the InCyte chip estimation system. This was done within the InCyte user interface, utilizing functions to input gate count, clock domain, memory, I/O and other design specifications. Using the InCyte IP browser, we selected and added IP to the design and selected the technology node, process, and libraries of choice to be included in the estimation. InCyte also supports bulk data import via Excel spreadsheet. This functionality was not utilized during the evaluation.

Within InCyte there is a comprehensive IP catalog, so we were able to include the exact 3rd party IP, targeted at TSMC, that had been used for each ASIC. In addition, we needed to incorporate Cisco- proprietary IP used within the designs. This was done with relative ease, using the tool's capability to add proprietary IP to be described and included in the IP catalog. The Cisco IP used in both designs was readily integrated for inclusion in our evaluation.

The InCyte chip estimation system allows for estimation of chip die size, active power, static leakage power, yield, and packaged chip cost. For this benchmark, we decided to focus specifically on die size estimation.

InCyte allows for a comprehensive set of inputs to define the chip specification on which an estimate is based. To perform the evaluation, we input the technology node, standard cells, memories, I/O's, and hard and soft-IP used in the respective chips we were using for our evaluation. The description of the level of information included is listed below by category.

Technology - Definition of the underlying foundry process used to fabricate the chip, including technology node, process variant, and number of metal layers.
Standard Cells - Core library cells to be used for logic blocks (including RTL and Soft-IP macros).
I/O Frame - I/O Pad cells and bonding rules for on and off chip connections.
Memories - Specific size and type of memories used.
Hard-IP - Hardened macro cores, either sourced from the integrated catalog including digital, mixed signal, and analog macros, or based on internal IP. Choices limited to IP available within current technology node and process choice.
Soft-IP - Synthesizable cores, either sourced from the integrated catalog or based on internal IP.

Once we had input our complete specification into InCyte, we launched the estimation process. Estimations took between 3 to 10 seconds on average.

The tool utilizes a set of pre-compiled models based on design kit data provided by IP suppliers and foundries to enable accurate silicon estimations based on a high level design specification. Users can add additional data models for other process technologies and IP data not already integrated into the system.

These models factor in size, power, leakage, and other information for various design components, such as standard cell and I/O libraries, from the same data files utilized by other implementation tools including Synopsys Liberty files and Cadence LEF files.

InCyte's die size estimation algorithm is a frequency based utilization model. Die size for each block in the design is calculated based on a number of factors including the standard cell library of choice, frequency and block specific components as well as the technology node, foundry, and process technology chosen. An I/O ring is then created based on the I/O components chosen.

Macro models of memory compilers enable InCyte to accurately estimate size, power, leakage, and performance of memories, effectively emulating a memory compiler from a 3rd party or internal vendor. InCyte comes bundled with memory models from leading suppliers. Additional models can be created with Chip Estimate's modeling software.

InCyte reports results in a datasheet report format. Results can also be exported into a CSV (comma separated values) file. A seed floorplan is also generated which is size and hierarchy accurate, including a fixed I/O ring. This floorplan can be exported in LEF/DEF format to interface to existing implementation tool flows.

InCyte's datasheet results include detailed size, power, and leakage analysis for each component in the design as well as the core and I/O areas. The tool reports core or I/O bounding and breaks down power and leakage by block and individual components. Graphical charts are also available to describe die area usage.

The InCyte system also offers the user access to tune models to enhance accuracy. Having the ability to tune models was key in our consideration of the tool. The parameters and models within InCyte that can be tuned include:

Technology
Layout
Utilization
I/O
Memory
Hard-IP
Soft-IP

We didn't tune any of these default models, but model tuning offers Cisco the ability to attain even better results once familiar with InCyte. We anticipated tuning models based on internal knowledge and experience with our designs.

3. SILICON RESULTS VS ESTIMATION

Bridge ASIC
In this benchmark, we compared core area, and looked at memory, macro and standard cell area, utilization, and blockages. The correlation between the actual silicon produced and the InCyte estimate was very good, and it required only minutes to enter the design specifications into the tool. InCyte estimated the chip at 6.7% larger than actual, slightly pessimistic. A table summarizing the actual silicon vs. the InCyte estimation results is below.

Bridge Silicon vs. InCyte Estimate

(mm2 for area units)	Actual	InCyte
Memory area + halo	89.750	92.000
Misc. macro area	0.654	0.600
Total blockages	3.000	3.000
Total standard cell area	86.446	96.400
Total Core Area	179.850	192.000

The die size correlation for this design
met the Cisco stated goal.
PORT ASIC
As with the Bridge design, in this benchmark we compared core area, and looked at memory, macro and standard cell area, utilization, and blockages. The correlation between the actual silicon produced for the PORT and the InCyte estimate was again very good; InCyte estimated the chip at 7.2% larger than actual. A table summarizing the actual silicon vs. the InCyte estimation results is below.

PORT Silicon vs. InCyte Estimate

(mm2 for area units)	Actual	InCyte
Memory area + halo	33.160	35.320
Total blockages	2.000	2.000
Total standard cell area	85.650	92.108
Total Core Area	120.810	129.500

The die size correlation for this design
met the Cisco stated goal.
5. SUMMARY AND NEXT STEPS

We were impressed with the accuracy achieved with InCyte. The system also enables tuning of models over time so that an even higher correlation with silicon may be achieved.

Overall, based upon our analysis, InCyte consistently shows over 90% accuracy in die size estimation when compared to final silicon.

The benchmark analysis convinced Cisco that with InCyte, more consistent estimation results with a much tighter correlation with silicon could be achieved. InCyte also has built in flexibility that will enable us to tune the system so estimations are influenced by operating conditions, and by our general knowledge gained through experience with the system.

Another factor in our consideration and ultimate recommendation of InCyte was ease of use and maintenance of system to ensure current IP modeling. As mentioned earlier, as part of our evaluation we had integrated our IP into the InCyte IP catalog. Our in-house method was difficult to keep current, and as the estimation support and maintenance was not centralized, we ran the risk of different estimates using different generations of models. This problem would be mitigated with InCyte, both for process data, vendor IP, and also when we needed to add updated and new Cisco-proprietary IP to the catalog.

Another key factor in our recommendation of InCyte was the system's ability to enable rapid "what if?" analysis. With estimations taking a few seconds to complete, our designers and system architects can make micro or macro modifications to their design specifications to assess the impact to die size, power, and downstream chip cost. This can be minor modifications such as increasing a clock speed to quantify the impact on power, or large scale changes such as migration to other technology nodes or process technologies. Using InCyte, we will be able to perform multiple estimations using libraries and IP with diverse performance and density attributes. We believe having this capability will further contribute to our goal of planning for the best design - and then achieving it.

Language:

English |

Japanese |

Chinese

Feedback Privacy Policy Terms of Use Newsletter & Tech Talk Archive IP Catalog Site Map