Real-Time Detection of Solder Joint Faults in Operating FPGAs
By Ken Harris
Senior Technical Writer
The Problem: Solder Joint Faults in FPGAs
Solder joint faults can be described
with a single word - pernicious. Solder joints connect the BGA package,
containing a FPGA processor, to the PCB. Without early detection, electrical
anomalies caused by solder joint faults can result in the catastrophic
failure of mission-critical equipment. To prevent this, Ridgetop Group,
Inc. designed the SJ BIST™. Part of a line of electronic prognostic
solutions, the SJ BIST provides real-time detection of solder joint
faults in operational FPGAs.
Solder joint faults occur in the FPGA
(Field Programmable Gate Array) processors found in all types of commercial
and defense products. When embedded in BGA (Ball Grid Array) packages,
FPGAs become susceptible to failure from solder joint faults. The causes
of solder joint faults cannot be isolated, early detection is difficult,
and the intermittent failures escalate in severity until devices are
rendered unreliable or inoperable. But, as so often seems the case,
the problem is the solution.
In operational devices, the primary
contributors to solder joint faults are thermo-mechanical and shock
stresses. Whether from vibration, torque forces, thermal cycling, material
expansion, or environmental stresses, the inevitable result is mechanical
failure from cumulative damage. At the solder joint level, the damage
is seen as a crack at the package/PCB (Printed Circuit Board) boundary
although there are other possible points of failure in the solder joint
Statistical degradation modeling is
the current method for predicting solder joint faults in programmed,
operating FPGAs. But, since statistics vary and work best at trending
large populations, statistical degradation modeling is a stop-gap solution,
at best. With SJ BIST (Solder-Joint Built-In Self-Test), Ridgetop Group
provides a true tool for direct, in-situ measurement of prognostic indicators
of faults in solder joint networks.
Since solder joint faults develop
during manufacturing as well as in the field, SJ BIST can detect faults
in uninstalled FPGAs. These manufacturing-related faults have their
own set of detection challenges. Visual inspection is the current method
used for identifying faults in the manufacturing environment. The primary
disadvantage is the inability to test and inspect the solder joints.
Visual inspection is limited to the
outer row while the board size and other surface-mounted components
limit the view even further. As the array density of BGA packages increases,
alignment tolerances become tighter. In fine pitch BGAs, there are thousands
of solder balls with a 1.0 mm pitch and a 0.60 mm ball diameter. Under
these conditions, pad misalignment and insufficient solder become causes
of open and partial-open faults. Even a 100% inspection by X-ray is
not guaranteed to find solder joint faults when solder does not wet
the entire pad. Another defect, involving the solder ball and paste
wicking into a plated through hole is not readily identifiable even
with X-ray imaging. When enough solder wicks into a hole, an open is
created for that lead.
As an in-situ softcore, SJ BIST is
ideally suited for PCB-FPGA reliability testing in manufacturing
An industry standard defining BGA
package failure involving thermal cycles, with or without accompanying
physical stresses, is the occurrence of:
A high-resistance spike
of 300 ohms or higher for a duration period of 200 nanoseconds or longer.
Ten or more events that
occur within ten percent of the time (number of thermal cycles) of the
Types of Solder Joint Failures
- Solder Ball Cracks
Over time, solder joints can develop
cracks from cumulative stress damage. Cracks typically appear in the
package/PCB boundary. A crack can cause the partial separation of the
solder ball from either the BGA package or the PCB. One typical location
for a crack is between the BGA package and the solder ball. Another
typical location for a crack is between the PCB and the solder ball.
Progressive damage to a cracked solder ball leads to another type of
failure - the fracture.
- Solder Ball Fractures
Once a crack develops, progressive
stresses can cause more damage leading to a fracture. A fracture is
the complete separation of a solder ball that breaks that point of contact
between a BGA and PCB.
As existing fractures remain open
for longer periods, contamination or oxidation coats the fracture surfaces.
This eventually creates a failure progression from degraded joints to
intermittent opens of short duration (nanoseconds) and then relatively
long durations (microseconds).
- Missing Solder Balls
The progressive mechanical
stresses that lead to a crack to form a fracture end in displacement.
A displaced solder ball not only results in a permanent failure for
that pin, the highly conductive ball could be lodged in another location
and cause an unwanted short in another circuit.
- Intermittent Signals
Intermittent signals are caused by
solder ball fractures that periodically open and shut. Vibration, motion,
thermal, and other stresses cause conditions where a solder ball can
move enough to open or shut a fracture. The flexible materials used
in PCB fabrication make intermittent signal failures possible. As vibration
stress, for example, causes a fracture to open and shut, the circuit
of that solder ball unpredictably opens and closes resulting in an intermittent
The intermittent nature of solder
joint failures makes faults hard to diagnose. Also, the input and output
buffer circuitry of an I/O port makes it impossible to measure the resistance
of a solder point network belonging to a programmed, operational FPGA.
Often, a bench-tested assembly passes as No Trouble Found (NTF) because
damaged joints make temporary contact.
The Solution: The SJ BIST Innovation
Prior to the Ridgetop Group's innovation,
there were no known methods for detecting stress faults in operational,
fully-programmed FPGAs. The visual inspection, x-ray imaging, and reliability
tests used in manufacturing are ineffective because electrically-based
defects are essentially invisible in powered-down devices.
Through early detection of impending
faults, SJ BIST supports condition-based maintenance and reduces intermittent
failures. Its outstanding sensitivity and accuracy allows the SJ BIST
to detect and report high-resistance faults as low as 100 ohms as fast
as a one-quarter to two clock cycles with no false alarms. Developed
as a large-scale solution, it attaches to the customer's existing,
built-in, test backbone. Due to its scalability, there is no point of
Ridgetop Group's SJ BIST is a licensable
IP core, part of the InstaBIST™ library, and requires no tools or equipment
to install. As a Verilog softcore synthesized into a customer's FPGA,
SJ BIST is minimized for the thrifty designer. Conscious of ever-shrinking
real estate, the only additions are small capacitors to the PCB and
a small code base to the existing test program. Under certain conditions,
the capacitors may not be required.
The Solution is the Problem
So, just how does SJ BIST work? As
mentioned before, the problem is the solution. The same electrical changes
in solder joints causing faults can be exploited to indicate accumulating
damage and prognose failure conditions well before catastrophic failure.
The shortcoming of the current detection methods is in their indirect
approach to assessing what is happening electrically. Visual inspection,
x-ray imaging, and failure analysis modeling are indirect, imprecise,
and non-specific at the individual fault-level.
In contrast, SJ BIST directly and
in real-time, measures and records the electrical properties of dedicated,
operational pins and solder joints. This method detects and recognizes
signal characteristics or changes indicating damage prior to catastrophic
failure. To put this concept another way, SJ BIST is analogous to an
A Real-World Analogy - the EKG
The EKG (electrocardiogram) measures
and records the electrical activity of the heart. Abnormalities in the
cardiac signal are seen in real-time and, naturally, while the heart
is in operation. While this alone is a great advantage over reliance
on indirect measurements, such as blood pressure or osculation, the
EKG has an even greater ability - prognosis. Libraries of cardiac
signals document the early electrical characteristics of heart conditions.
So, before a heart condition can be felt from performance degradation,
changes in electrical activity are detected, analyzed, and correlated
against a library of signal abnormalities to provide a prognostic determination.
This technique, when applied in medical science, has led to the advance
warning of many serious, even life-threatening, conditions and extended
SJ BIST - In Your World, In Your Business
Like the EKG, SJ BIST works in a similar
manner and its benefits for extending the operational life of electronic
devices is equally impressive. The InstaBIST library developed by Ridgetop
Group makes solder joint fault prognosis possible. Through direct analysis
of the real-time electrical activity occurring in FPGAs, SJ BIST detects
the faults and the indicators of progressive fault conditions.
SJ BIST is an ideal solution for the
automotive, industrial, and aerospace markets and is already used by
Daimler-Chrysler and Raytheon Missile Systems. Medical electronic devices
are a natural fit. Pacemakers, neurostimulators, and other devices placed
directly in or near the heart, brain, and spinal cord require high-reliability.
Electronic prognostics from Ridgetop Group would enable safe removal
and replacement before problems could develop.
IP licenses for SJ BIST start at $50k
and include technical services for installation. Training, documentation,
service contracts, and other technical services are available.
Ridgetop Group is a privately-held
firm founded in 2000 to provide mission-critical electronic prognostic
tools, fault-to-failure progression libraries, and semiconductor IP
libraries through excellence in engineering innovation. Customers include
NASA, Honeywell, DARPA, NAVAIR, Raytheon Missile Systems, Daimler-Chrysler,
ATK/Mission Research, General Dynamics, US Department of Energy, Air
Force Research Labs, and other government and commercial firms in North
America, Europe, and Asia.
is the senior technical writer at Ridgetop Group. An expert in usability
and cross-cultural communication, he has served as plenary speaker and
symposium chair for advanced topics in technical communication and information
design. Over a 25-year career, he has become an award-winning writer,
designer, and illustrator with awards ranging from academic contests
to juried national and international competitions. He received a BA
in English from the University of New Mexico, graduating cum laude and
with departmental honors. He has taught graduate-level technical writing
and graphic design at Georgia Tech and Southern Polytechnic State University
and is a senior fellow in the Society for Technical Communication.