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in the same bank quadrant can perform a row access. However, banks in the other three quadrants may be accessed during the interval row commands r1, r2, and r3 are directed to banks 1, 2, and 3, respectively.   Figure 3. Data transaction timing in micro-threaded DRAM core. After a column command ("c0x") is received, the selected column is accessed (column 0x of row 0 of bank 0). A time tCC must elapse before this bank can receive another column access command ("c0y"). However, banks in the other three quadrants may be column-accessed during the interval column commands c1x, c2x, and c3x are directed to banks 1, 2, and 3, respectively. As with the typical DRAM core example, the tCC interval is 4ns, and the bit transport interval is 0.25ns. However, each column access only transports data for half the tCC interval, and each column access only uses 8 of the 16 data links, resulting in a column granularity of 8 bytes, one-quarter of the previous value. The row granularity is 16 bytes, again one-quarter of the previous value. Reducing granularity in this way delivers performance advantages for applications in the groups mentioned previously, even though interface transfer bandwidth and core access intervals are unchanged compared to standard non-micro-threaded component. Figure 4 highlights the performance benefit of micro-threading, comparing two DRAMs featuring identical core and interface speeds operating in a graphics application accessing a range of triangle sizes. The micro-threaded core has two to four times the effective triangle access rate. Figure 4. Comparison of micro-threaded and non-micro-threaded DRAM performance. By adding this and other innovative features, future generations of the XDR memory architecture are capable of supporting data rates from 6.4GHz to 12.8GHz, thereby dramatically increasing the bandwidth to between 25.6GB/s to 51.2GB/s from a single x32 future generation XDR DRAM component. Search for Rambus IP here Conclusion; No Limits The XDR memory architecture continues to provide unprecedented levels of memory performance to keep up with processor performance requirements in next generation gaming, compute, and consumer platforms. Rambus innovations such as micro-threading effectively regain the memory bandwidth efficiency lost through successive generations of high-speed interfaces that have traded access granularity to gain improvements in maximum data rate. Continuing this trend, future demand for increased memory bandwidth will require further architectural innovations. Rambus is well placed to meet these requirements again going forward. About the Author