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Successful Third-Party IP Integration: Science or Art?

By Hans Bouwmeester
Open Silicon

The selection, procurement and integration of IP have become some of the biggest challenges in today’s ASIC and ASSP designs. Continuing efforts to reduce system costs, integrate more features and increase interconnectivity are increasingly making IP the bottleneck in achieving end-product cost and time-to-market goals. This article addresses the challenges facing today’s chip designers when it comes to successfully using third-party IP.

It is very common for IP to be procured from multiple vendors. Working with each vendor requires careful management of technical, quality, business and legal issues. Taking hard-IP as an example, modern ASICs often integrate multiple high-speed serial interfaces, such as PCIe, USB, and XAUI, memory interfaces such as DDR, CPUs such as ARM, MIPS, and Tensilica, and analog IP, including ADCs, DACs, PLLs, DLLs, and power management blocks, next to library and commodity IP that includes memories, IOs, and standard cells.

Various product development parameters, including time-to-market, cost, features, area, power and performance, drive selection of both technology and IP. For example, a low-voltage device with a unique interface may require a low-power technology, which means the unique interface IP that is needed now has the additional constraint of having to be available in that low-power technology. In addition, the risks associated with a possible lack of proven quality for that IP need to be weighed and taken into account when selecting the IP from various IP vendors.

Finally, as part of the IP selection-process, both compatibility and inter-operability need to be insured. For example, in TSMC’s 90G process multiple voltages can be supported for the IO oxide (1.8, 2.5 and 3.3V). However, not all combinations are supported at this technology node. The selection of IO libraries and PHYs needs to take this into account to ensure compatibility of the selected IP. Another example involves DDR PHYs and their associated controllers where interoperability concerns exist, especially in case when the DDR and the PHY are procured from different vendors, since the standard for the interface between them is new and may still be in flux.

As a result, selecting the best IP for such an ASIC has become a daunting task. Making the wrong choice can easily result in delays, cost overruns or, even worse, non-functional silicon.

The main goal for semiconductor companies in IP procurement is to acquire the IP at the best possible total cost of ownership. When weighing the costs, both direct "material" costs as well as more indirect costs need to be taken into consideration. Successful vendor relations management, careful selection of the engagement model and well managed business negotiations are key ingredients for a chip development organization to be successful in this area.

Direct costs associated with IP procurement from a third-party IP provider can comprise both up-front license fees and royalties. License fees are easy to take into account, since they are up-front and are known. Royalties, however, depend on the success of the chip developer in bringing a product to market and selling that product and represents a situation where both the chip developer and the IP provider share in the success of each organization.

Related to the direct costs, typical IP vendor engagement models include single and multi-use license models (with or without royalties), IP subscription models and foundry-sponsored IP models. Each of these has its unique application area along with pros and cons depending on the type of IP, the level of IP reuse and other factors. Also, per-part royalties can apply or be considered. In a royalty type of engagement, the vendor takes a share of the business risks in return for a payment for every chip sold, thereby allowing a lower license fee to apply which lowers the ASIC's development NRE costs at the expense of higher costs per part.

Another piece of the direct costs is related to the support and maintenance services as provided by the IP vendor. Unsupported IP has limited value and can actually cause a design team to come to a complete stop over an IP-related issue. Maintenance is required in order to make sure the vendor will release fixes and updates of the IP in situations where bugs are found or, in the case of hard IP, when the underlying process technology is updated by the foundry, resulting in an update of the process design rules. Often, support and maintenance contracts expire after 6 or 12 months, which may impact program budgeting.

Very often business and legal problems represent the biggest stumbling block that the IP integrator must overcome. Included in these categories are term of contract, usage restrictions, payment terms, indemnity clauses, sublicensing rights, the rights to disclose certain views of the IP with third parties, royalty reporting requirements, audit agreements, warranties, liability limitations, cancellation terms, and support and maintenance terms. The amount of time needed for negotiation of these terms is often underestimated. IP procurement tasks can thereby unexpectedly get into the critical path of the project schedule causing delays.

After qualifying an IP vendor and the needed IP, the IP integrator then must successfully integrate that IP into the target chip design. Unfortunately, silicon-proven IP at the target process node does not guarantee success in a particular design. Since every chip represents a different system environment to the IP embedded in it, the integrator must have a very good working knowledge of that IP in order to successfully implement it into that chip.

Integrating hard IP can be particularly troublesome for integrators, since the timing associated with a hard IP macro is tightly tied to the process in which the chip containing the macro will fabricated. This requires a high level of integrator expertise to optimally couple the IP with the surrounding system, in other words, the chip. Having a wide range of experience with a particular type of IP core in various chip designs means that an IP aggregator is well positioned for assisting the integrator in selecting the optimal core for a particular design. In addition, the aggregator can help the integrator to overcome any problems that may crop up during the integration.

Open-Silicon has developed an IP aggregation model that addresses both the legal and business negotiations as well as the critical technical qualifications that are part of the successful selection and implementation of third-party silicon IP onto a chip. To help IP integrators make the right choices of IP and IP vendors, the IP aggregator has a dedicated and experienced IP team that works with many IP providers, continuously qualifying and updating a list of recommended IP. By working with both IP suppliers and integrators, the aggregator’s IP team identifies market needs for IP and focuses on early identification and development of IP to meet emerging standards. This helps the aggregator keep a step ahead of the curve in identifying, selecting and recommending IP to customers and allows the aggregator to match IP to integrators’ specific needs.

The specific advantages of an IP aggregator include the following:

• Through economies of scale, the aggregator can cost effectively develop and employ IP rating procedures and a quality-assurance (QA) platform, minimizing the need for integrator modification and enhancing chip performance predictability and reliability.
• Pre-negotiated contracts provide easy and cost-effective access to pre-qualified IP from a wide variety of vendors.
• Strong relationships with IP partners and deep understanding of the IP development and integration process ensures timely IP delivery and integration in the design phase, leading to predictable design and time-to-market schedules.
• Qualification of the IP with the proper process models, EDA tools, and design methodologies for each target silicon process and tool suite maximizes the IP’s reusability for customers.
• Simplified IP integration and the use of high-quality, silicon-proven IP enhances the chance of first-time silicon success.