Statistical Static Timing Analysis - A Better Alternative
Rakesh Chadha is Director of Design Technology at eSilicon Corporation
J. Bhasker is a distinguished author and expert in the area of hardware description languages and RTL synthesis
Traditionally static timing analysis (STA) is used to verify if a CMOS digital design can meet the target speed at various process and interconnect corners. In practice, the worst-case slow or best-case fast process and operating corner conditions typically used during the STA correspond to the extreme 3ω corners1. This forces overdesign, leaving a lot of margin on the table in terms of chip power, area and performance. As a result, most of the manufactured parts can operate at higher speed and dissipate much less power than the value supported by the package design.
Statistical static timing analysis (SSTA) helps address this problem, allowing the design team to make tradeoffs in terms of performance and the roll-off at the process extremes. An overview of the SSTA is presented in this article.
1. Variations in Process and InterconnectGlobal Variations in Process
The global process variations, also called inter-die device variations, refer to the variations in the process parameters which impact all devices on a die similarly. The models for the global process variations are intended to capture the variations from die to die. As an illustration, consider the variations of a global parameter value (say G_p1) shown in Figure 1. In practice, the G_p1 parameter may correspond to device threshold for a standard PMOS device. The parameter G_p1 being global, the PMOS devices in all cell instances of a die will correspond to the same value of G_p1.
Figure 1 Variations in a global parameter.
In the deterministic (that is, non-statistical) STA, the slow process models typically correspond to the +3ω corner condition and the fast process models typically correspond to the -3ω corner condition for the inter-die variations.
Local Variations in Process
The local process variations, also called intra-die device variations, refer to process parameter variations which can differently affect devices on a given die. The variations modeled here are intended to capture the random process variations within the die. This means that a local parameter may have different values on the same die. For example, different INV cell instances on a die may see different local process parameter values. This can cause different instances of the same INV cell to have different delay values even if other parameters such as input slew and output loading are identical. An illustration of the variations in the INV cell delay caused by global and local variations is depicted in Figure 2.
Figure 2 Delay variations due to global and local variation.
Even with deterministic STA, OCV (On-Chip Variations) analysis is used to account for variations in timing due to local process, power supply and temperature variations. The statistical timing models utilized for SSTA normally include the local process variations, thus the OCV analysis using statistical timing models should not include the local process variation in the OCV setting.
Variations in Interconnect
There are various interconnect corners which represent the extremes in parameter variations of each metal layer affecting the interconnect resistance and capacitance values. These parameter variations are generally the thicknesses of the metal, dielectric thickness, and the metal etch which affects the width and spacing of the metal traces in various metal layers. The statistical approach models all possible combinations of variations in the interconnect space and thus models variations which may not be captured by analyzing only at the specified interconnect corners. For example, it is possible that the launch path of a clock tree is in METAL4 whereas the capture path of the clock tree is in METAL2. Timing analysis at the traditional interconnect corners considers various corners which vary all metals together and thus can not model the scenario where the METAL4 is at a corner which results in max delay and the METAL2 is at the corner which results in min delay. Such a combination corresponds to the worst-case scenario for the setup paths and can only be captured by modeling the interconnect variations statistically.
2. Statistical AnalysisWhat is SSTA?
The modeling of variations described above is feasible if the timing for the cell and the interconnect parasitics are modeled statistically. This implies that the timing models are described in terms of mean and standard deviations with respect to process parameters (global and local). The interconnect resistances and capacitances are described in terms of mean and standard deviations with respect to interconnect parameters. The delays of each timing arc (cell as well as interconnect) are represented by mean and standard deviations with respect to various parameters. Every delay is represented by its mean and standard deviations (with respect to independent process and interconnect parameters modeled statistically). Apart from delay, the variations in the pin capacitance values at the cell inputs are also modeled statistically. The statistical static timing analysis (SSTA) procedure combines the delays of the timing arcs to obtain the path delay which is also expressed statistically (with mean and standard deviations). The SSTA maps the standard deviations with respect to the independent process and interconnect parameters to obtain the overall standard deviation of the path delay. For example, consider the path delay from two timing arcs as shown in Figure 3. Since each delay component has its variations, the variations are combined differently depending upon whether these are correlated or uncorrelated. If the variations are from the same source (such as caused by G_p1 which track each other), the ω of the path delay is simply equal to (ω1 + ω2). However, if the variations are uncorrelated, the ω of the path delay is equal to sqrt(ω12 + ω22) which is smaller than (ω1 + ω2). In practice, the variations modeled fall in both categories - correlated as well as uncorrelated and thus the contributions from these types of variations need to be combined appropriately.
Figure 3 Path delay comprised of variations in components.
The clock path delays for launch and capture clock are also expressed statistically in the same manner. Based upon the data and clock path delays, the slack is obtained as a statistical variable with its nominal value as well as standard deviation. Assuming normal distribution, effective minimum and maximum values corresponding to (mean +/- 3ω can be obtained. The mean -/+ 3ω corresponds to coverage of 99.73% of the distribution which means that only 0.135% of the resulting distribution is smaller than the (mean - 3ω) value; similarly only 0.135% of the distribution is larger than this (mean + 3 ω) value. The designer can choose to cover smaller (or larger) proportion of the distribution based upon the statistical signoff being smaller (or larger) than the 3ω. For example, 99% of the coverage of the distribution correspond to -/+ 2.576 ω of the distribution.
Based upon the path delays, the SSTA reports the mean, standard deviation and the "effective minimum / maximum" values (based upon the coverage of the distribution) of slack for each path whereby the passing or failing can be determined based upon the required statistical confidence.
Statistical Timing Libraries
In the SSTA approach, the cell libraries used in a design provide timing models at various environmental conditions. For example, the analysis at max Vdd and low temperature corner utilizes libraries which are characterized at this condition but the process parameters are modeled statistically. For N process parameters, a statistical timing library characterized at power supply of 1.32V and -40C may include the following:
Timing models with nominal process parameters, plus the following with respect to each of the process parameters.
Timing models with respect to one parameter with variation (nominal + 1ω), the other parameters being at nominal value.
Timing models with respect to one parameter with variation (nominal - 1ω), the other parameters being at nominal value.
The results from statistical analysis provide path slack in terms of its mean and corner values. The SSTA reports indicate whether the mean as well as the statistical extremes of the path slack meet the requirements. An example of the path slack distribution is illustrated in Figure 4. The path slack has a mean value of +0.72ns with 0.28ns standard deviation. Assuming -/+3ω coverage, the effective minimum value has a violation by 0.12ns - path slack minimum is -0.12ns. If +/- 2.576ω coverage is selected, the statistical distribution meets the requirement (no negative slack). The +/- 2.576ω coverage implies that only 0.5% of the manufactured parts will have a timing violation.
Figure 4 Path slack distribution.
With the statistical models for the cells and interconnect, the statistical timing approach analyzes the design at corner environment conditions and explores the space due to process and interconnect parameter variations. For example, a statistical analysis at worst-case VT (Voltage and Temperature) would explore the entire global process and interconnect space. Another statistical analysis at the best-case VT (Voltage and Temperature) would also explore the entire process and interconnect space. These analyses can be contrasted with the traditional corner analysis at worst-case (or best-case) PVT each of which explore a single point of PVT and interconnect.
Rakesh Chadha is Director of Design Technology at eSilicon Corporation. He is an expert in timing and signal integrity, having over 25 years of experience at companies like eSilicon, Bell Labs and Cadence. At Bell Labs, he was responsible for Sematech projects on Chip Parasitic Extraction and Signal Integrity Verification. He has led complex ASIC projects at eSilicon pertaining to 130nm, 90nm and 65nm technologies. Rakesh has been featured over 25 times in various publications and journals, and holds a US patent related to Signal Integrity. He is a co-author of a book entitled Computer Aided Design of Microwave Circuits (Artech House, 1981).
J. Bhasker is an expert in the area of hardware description languages and RTL synthesis, and has had numerous articles published related to these topics. He has also been a distinguished member of the technical staff at Bell Laboratories. Bhasker has been featured in various industry papers, journals, conferences and publications, focusing mostly on design automation and high-level synthesis algorithms. He has been the chair of two working groups: the IEEE 1076.6 VHDL Synthesis and the IEEE 1364.1 Verilog Synthesis. Bhasker was also a major contributor to the IEEE Std 1076.3 NUMERIC packages. Furthermore, he was awarded the IEEE Computer Society Outstanding Contribution Award in 2005.