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Adding Physical Test and Debug Access to Chips with a Compact JTAG Core
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Pierre-Xavier Thomas — IPextreme

Compact JTAG (cJTAG) IEEE 1149.7 is an emerging standard that extends the IEEE 1149.1 JTAG (Joint Test Action Group) standard. With JTAG, a value could be forced on an I/O pin on one chip and then sensed on a chip connected to it, proving that the PC board trace was intact. This came to be called "boundary scan", because the entire boundary of each chip could theoretically be tested by scanning values onto the I/Os and detecting the values on the chips to which they were connected. Although JTAG was originally intended to test connections outside a chip, it was also useful for testing the internal functionality of the chip, so JTAG essentially became an auxiliary port into a chip for testing and instrumentation purposes.

The next-generation standard, cJTAG, defines test and debug capabilities that are a complementary superset of the JTAG standard, expanding the standard in the areas of system awareness, capability, and pin efficiency. The cJTAG IEEE 1149.7 standard defines three layers of capabilities: compatibility with the JTAG standard; extensions to the standard JTAG protocol; and advanced 2-pin operation. Ensured compatibility allows JTAG and cJTAG to work together in the same chain, and such added capabilities as star, or multi-drop, interconnection make implementation easier and enable parallel testing. Reducing the required pin count from 4 to 2 can decrease device pin count, or allow the two extra pins to be used for other functions, which can be important in new generations of SoCs, which typically have tight pin budgets. These features are grouped into cJTAG classes T0 - T5.

cJTAG Classes

Each of the 6 cJTAG classes builds on the capabilities developed in the previous class. Classes T0 - T3 ensure compatibility with the IEEE 1149.1 JTAG standard and extend the TAP (Test Access Port) protocol to support additional functions. The last two classes (T4 and T5) implement advanced features, such as 2-pin operation, additional optimized scan formats, and instrumentation channels to support non-scan transfers. This grouping of capabilities enables a step-by-step deployment of the standard, and enables designers to use the capabilities of the standard that are necessary according to their device requirements. For example, one may decide to use the 2-pin operation available at class T4, but not the instrumentation channel capability from class T5.

Class T0
Class T0 ensures JTAG-compliant behavior after a Test-Logic-Reset when multiple TAPCs (Test Access Port Controllers) exist on a chip.

Class T1
Class T1 adds support for the IEEE 1149.7 cJTAG command protocol, which enables the advanced capabilities of the subsequent classes. It also provides the ability to generate functional and test resets. Power-down mode control is added to enable the power-down debug and test logic when not in use, providing a means for low-power design.

Class T2
Class T2 adds the ability to bypass a chip's System Test Logic from a system scan chain, resulting in a 1-bit path for IR (Instruction Register) and DR (Data Register) scans and providing a mechanism to speed up access to a specific device. An option to use chip bypass at start-up is provided to support the physical connection of a DTS (Debug Test System) to a running system without corrupting its operation (Hot-Connect Protection).

Class T3
Class T3 adds support for connecting TAP controllers in a 4-wire star scan topology (TAPCs connected in parallel). Direct addressability of cJTAG TAP controllers is added, along with a means to synthesize the equivalent of series scan operations in a star scan topology, so that all operations appear as series scan from the BSDL (Boundary-Scan Description Language) perspective (Figure 1).
cJTAG class T3 topology chart

Class T4
Class T4 adds support for advanced scan protocols to maximize scan performance and 2-pin operation (all signaling done using only TMSC and TCKC pins, which means TDOC and TDIC can be removed or used for other functions). A class T4 TAP supports either a narrow (2-wire operation) or a wide (4-wire operation) implementation, allowing designers to save pins on their devices. To maintain (and for some use cases, to improve) the overall performance for the 2-pin operation, the clock rate can be doubled.

Class T5
Class T5 adds support for up to 8 data channels for non-scan data transfers, and gives the TAP the ability to concurrently perform debug and instrumentation operations, which reduces the need for dedicated pins for instrumentation. This improvement is made possible because the non-scan data are transferred during idle time. Data channels can be used for application-specific debug and instrumentation purposes.

cJTAG Silicon IP

Texas Instruments has been driving the IEEE 1149.7 cJTAG standard, and has made its implementation available for licensing through IPextreme. IPextreme is a semiconductor IP company that productizes, markets, and supports famous IP originally developed by integrated device manufacturers. The first version of the cJTAG-IEEE 1149.7 is available now and supports all mandatory and optional class T0 - T4 features.

Like all IP cores available from IPextreme, the cJTAG IP is distributed with a complete set of deliverables, including the source code and its configuration matrix, implementation scripts with IO constraints and timing exceptions, an integration test bench and example test suite, and comprehensive documentation.

Source Code and Configuration
The cJTAG IP core is written in Verilog and offers one hardware configuration parameter, power-down support (PDM_SUP). When PDM_SUP is selected, the IP supports the power-down modes from class T1, and requires a 32-kHz input clock. The IP is partitioned following the description of the IEEE specification, where the EPU (Extended Protocol Unit) implements the extended control protocols state machine (figure 2). The APU (Advanced Protocol Unit) implements the class T4 and T5 features. The RSU (Reset and Selection Unit) functionality as described in the cJTAG specification is included in the APU block. Additional infrastructure blocks (Clock and Reset Generation Logic) are included to condition the reset and clock signals to the IP and to the rest of the System Test Logic.
cJTAG IP Configuration chart

Implementation scripts, along with I/O constraints and timing exceptions, are provided for the main EDA tool flow. The IP core is fully synthesizable and technology-independent, and is scannable if it needs to be part of the chip scan chain. A small part of the logic in the reset and clock generation modules is not scannable, and can be disabled in scan mode by the use of the test_mode input signal (part of the DFT interface).

Although higher frequencies can be easily reached by synthesis, the frequency of operation for the TCK is recommended to be set below 50 MHz, to take into consideration pads and system board delays. When the PDM_SUP hardware parameter is set, an additional 32-kHz clock is required for power-down condition detection. If the IP is put in the chip scan chain, the test_clock (part of DFT interface) can be set to the same frequency as the TCK.

The initial cJTAG implementation accounts for around 2500 equivalent gates for classes T0 - T4. Support of class T5 features will increase its size.

Integration Test Bench and Tests
The purpose of the ITB (integration test bench) is to provide an example of how to integrate the cJTAG IP core into a system. The provided example tests demonstrate initialization sequence, configuration, and basic functionality of the IP in an example system environment. Although some components of the ITB can be used as a starting point for building up a system verification environment, the purpose of the ITB and its tests is not to provide the verification environment with its complete test suite.

Integration Considerations

The cJTAG IP is inserted between the off-chip DTS and the on-chip STL. The STL consists of one or more JTAG TAPCs. The debug and test interface becomes the cJTAG interface. Consequently, any IC using the JTAG interface may use this standard to reduce the test interface pin count from 4 or more pins to 2 pins. Figure 3 illustrates an SoC implementing a 4-wire cJTAG interface
4-wire cJTAG Implementation chart

cJTAG-IEEE1149.7 interfaces and integration in an SoC

The cJTAG interface is the IEEE 1149.7 Test Access Port brought at the chip level to connect to a DTS. Only the TCKC and TMSC signals are necessary for 2-pin operation. TDIC and TDOC are for 4-pin operation, or for auxiliary functions in 2-pin operation. TRST and RTCK are optionally connected, depending on the device requirements.

The DFT interface is connected to the DFT interface if the IP is put in the chip scan-chain. The chip power-on reset and the optional 32-kHz clock required when the power-down modes are supported go to the clock and reset generation block, which conditions the reset and clock signals used inside the IP and sent outside to the rest of the chip logic.

The Configuration interface is used to configure the IP core according to the requirements of the chip it is integrated into.

The IEEE 1149.1JTAG interface connects to the STL on the chip. The STL may have one or more IEEE 1149.1 TAPs. The JTAG interface signals are TCK, TMS, TDI, TDO, and (optionally) TRST. Optionally, RTCK can be used by the DTS, in which case RTCK is first returned from the STL to the cJTAG through this interface.

The System and Power interface is to be connected to the Reset and Power Management modules of the device when the functional reset and power-down modes are supported by the system. When configured to support power-down modes, the cJTAG IP core detects power-down conditions as described in the IEEE 1149.7 specification, depending on the selected power-down mode (configured by the DTS), and issues a request to the chip Power Management module when enabled. The Power Management module is responsible for shutting down the relevant logic based on this request. Similarly, the cJTAG issues a functional reset to the chip Reset module when it detects a functional reset sequence on its IEEE 1149.7 interface. The Reset module needs to acknowledge the reset request to the cJTAG IP state machine, and is responsible for broadcasting the adequate functional reset to the relevant part of the chip.

System integration and chip-level pad requirements

cJTAG allows the mixing of topologies and technologies using the same interface (Figure 4). Chip architects can select the number of pads dedicated to the test and debug interface depending on how the chip is intended to be deployed in a system.
Illustration of mixing topologies and technologies using cJTAG chart

cJTAG Enables Better Performance at Lower Cost

The IEEE 1149.7 cJTAG standard defines a framework and mechanisms, building on the IEEE 1149.1 JTAG standard and preserving the hardware and software investment made around JTAG Boundary Scan. It provides all the mechanisms for better performance and lower power at lower cost, with more functionality, including:

  • 2 pin-operation and 4-pin operation
  • Functional reset capability from a protocol sequence
  • Test reset (TRST) capability from a protocol sequence (no need for a dedicated pin)
  • Power management of the TAP controllers capability from protocol sequence
  • Series and a new star topology to increase debug performance and resolve wire routing issues encountered in multi-chip modules and stacked-die devices
  • Chip-level "Super Bypass" to remove a chip from a system scan chain and further increase debug performance

Depending on the target systems and their test and debug strategies, a chip architect may decide to make the device participate in a 2-wire and/or 4-wire branch, in a series and/or star topology. Deploying a 2-wire star topology-based system requires the availability of the devices from the bill of materials to be IEEE 1149.7 class T4 capable.

The first cJTAG IP core, as made available by IPextreme, is a fully synthesizable and technology-independent small IP core that does not require any special pads. Its integration is compatible with IEEE 1149.1, which considerably limits the risk of deployment in a new device as it expands its debug and test capability and potential from a known state.

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About the Author

Pierre-Xavier Thomas

Pierre-Xavier Thomas is an industry value chain expert with experience at semiconductor, EDA and system companies. Before joining IPextreme, Mr. Thomas managed teams and was an architect for the design of SGI supercomputer hub chips, following a similar role at Clearwater Networks. Previously, he managed development for Synopsys' DesignWare IP library, including leading the team that developed and commercialized the first Synopsys Multimedia IP. Mr. Thomas started his career with ST Microelectronics as part of the team who designed the first MPEG Video Encoder System. Mr. Thomas holds a Diplome d'ingenieur from the University of Technology of Compeigne (UTC-France) and a Diploma d'Etude Appronfondie in Signal, Image and Speech Processing from the National Polytechnic Institute of Grenoble (INPG-France).