TLM-2.0 in Action - Welcome to the New
World of Model Interoperability
By Mike Meredith President, Open SystemC Initiative
It's been nearly a year since the Open SystemC Initiative (OSCI)
introduced the TLM-2.0 (transaction-level modeling) standard at DAC,
representing a significant milestone in model interoperability and IP
Providing an essential framework for system-level
design, the new interfaces for transaction-level modeling with SystemC
make seamless model exchange within companies and across the IP supply
chain for architecture analysis, software development and performance
analysis, and hardware verification viable, while at the same time
creating a robust modeling foundation for virtual prototyping.
Today, TLM-2.0 models are being widely used both as a
modeling standard and interoperability standard, and have been
embraced by the entire design ecosystem including systems and IC
companies, IP vendors, and EDA suppliers.
When the group started out four years ago, there was
broad agreement that the industry needed standards-based modeling
guidelines. In the run-up to standardization last year, we held a
public review that generated more than 2,100 comments and suggestions
to help make TLM-2.0 better, stronger, and more user friendly. Even
more impressive, more than 7,000 engineers have downloaded the
standard in the past year.
Demonstrating the importance of SystemC and TLM-2.0
throughout the worldwide design community, an international network of
SystemC user groups in Japan, India, Europe, South America, and North
America report phenomenal growth in SystemC design in all regions,
accompanied by ready adoption of the TLM-2.0 standard for SoC
Acknowledging that user demand for more detailed and
practical information continues to grow, we recently launched an OSCI
first: a free, online video tutorial from leading TLM-2.0 experts
posted on our website: http://www.systemc.org/news/events/tlm20tutorial/.
Presented as part of the technical program at the Design and
Verification Conference (DVCon) held earlier this year, the tutorial
features SystemC experts from Intel, Synopsys, Doulos, and XtermeEDA
who delve into the fine points of the OSCI TLM-2.0 standard while
providing practical information on the creation and adoption of
TLM-2.0 models. The tutorial's examples-based and in-depth format has
had phenomenal response, with more than 500 people from all over the
world viewing the tutorial within days of its being posted. The
tutorial is approximately three hours long. It can be viewed at any
time of the day and in short durations.
To see how far we have come, it's useful to take a
look back at the development of the TLM-2.0 standard which perfectly
illustrates the importance of colleagues from diverse backgrounds
coalescing around a common goal to advance the science of IC design
while expanding market possibilities for all.
As model interoperability became a necessity it was
imperative to define and support a viable standard to address the
issue. OSCI's TLM Working Group consists of a cross section of ESL,
EDA, IP, Semiconductor, and Systems experts.
When this effort began, the main goal was to
standardize the way models communicate. We achieved that while finding
a way to satisfy key performance requirements. In December 2006, OSCI
announced the delivery of the Draft SystemC TLM-2.0 kit, containing
proposed extensions to OSCI TLM application programming interface
(API) standards, an open-source library implementation, and
interoperable modeling examples. Since then, the scope of the standard
has been expanded. It is more cohesive, and where possible, simplified
to include more thorough documentation and improved examples.
The extended APIs provide a fundamental,
general-purpose interoperability layer. A specific payload, to be used
in conjunction with these interfaces, helps achieve a higher degree of
interoperability when generically modeling memory-mapped, bus-based
components. Over time, this generic payload has been simplified, and
the efficiency of the mechanism for extending it has been improved.
After a successful public review period of the TLM-2
draft 2 kit ending January 31, 2008, feedback from companies
throughout the worldwide SystemC ecosystem offered significant ideas
for improvement. OSCI was committed to reviewing and addressing all
suggestions received in this process. Experts from over 18 SystemC
user companies, ESL tool developers, and IP providers provided their
input to refine the interoperability benefits of the emerging
As the standard progressed, several features were
added to boost simulation performance enabling what we call "speed
interoperability" in addition to "model interoperability" for SystemC
virtual platforms. Temporal decoupling allows initiator models, such
as instruction set simulators, to run ahead of the SystemC kernel and
synchronize only periodically to significantly reduce the required
number of costly context switches. The addition of the direct memory
interface allows interconnect models to be bypassed, facilitating
high-speed access to modeled memory, and a dedicated transaction debug
interface ensures that debugging is an integral part of a system model
while enabling debug activity without interference with the system
OSCI is currently developing a SystemC TLM-2.0
language reference manual (LRM) that will ultimately be used to drive
the IEEE standardization process for TLM-2.0.
As we head into DAC it is very gratifying to see the
impact TLM-2.0 is having on so many designs in so many areas around
the world, while continuing to nurture and grow broad industry support
for the standard. We will be celebrating these accomplishments at the
show, and revealing the latest progress on our continuing
standardization efforts during the North American SystemC User's Group
(NASCUG) meeting, co-located with DAC. (http://www.systemc.org/news/events). The event is
free with registration.
I look forward to seeing all of you there, and thanks
for your ongoing support of OSCI and open standards.
About the Author
Mike Meredith is currently the Vice President of Technical Marketing for Forte Design Systems and serves as the president of the Open SystemC Initiative. His more than 20 years EDA experience includes development of printed-circuit board layout, schematic capture, timing-diagram entry, verification and high-level synthesis tools. Prior to that he spent 10 years doing embedded design in the biomedical and industrial automation industries. He is a contributor to two books on ESL methodology and high-level synthesis and is the holder of 3 U.S. patents in the areas of timing diagrams and timing analysis of electronic circuits.