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Metric Driven Verification Key to Delivering High Quality SuperSpeed USB (3.0) IP

Pete Heller, Product Line Manager
Cadence Design Systems

Quality Will be the Differentiator in the Crowded SuperSpeed USB Market
Verification quality and predictability is simply not an option to succeed in the already crowded SuperSpeed USB 3.0 IP market. SuperSpeed USB, ratified by the USB Implementer's Forum only in Q4'08, is expected to rapidly gain traction in the market. The number of design teams implementing SuperSpeed designs bears this out. Cadence is already aware of over 40 teams (including both captive and commercial providers) developing SuperSpeed USB IP and there are most certainly more to come. To stand out in such a crowded market will require superior quality.

SuperSpeed USB offers up to 10X higher throughput while simultaneously reducing power consumption. Such an undeniable value proposition, taken together with the massive USB installed base and growth rate (in excess of 6 billion units and growing at 2+ billion units per year), have positioned it for rapid adoption. SuperSpeed USB's value proposition is even more compelling given the range of potential new applications it can serve. For example, while USB 2.0 has made significant inroads into external hard drives, SuperSpeed USB provides the throughput and lossless data attributes required for internal drives. In other words, among other potential new applications, SuperSpeed USB may be able to displace SATA controlled drives.

With so many IP vendors eyeing the opportunity outlined above it is evident that a race is now on to deliver SuperSpeed IP in 2009. Since IP integrators will have the luxury to select IP from a broad set of vendors it will be crucial for IP developers to ensure the highest quality in order to differentiate. To achieve this will require near flawless execution. I.e., the key for IP developers is to apply their design and verification resources most effectively and efficiently.

Traditional approaches to IP verification are simply no longer up to the task of verifying such substantial layered, high speed serial protocols such as USB 3.0, PCI Express 3.0 or MIPI UniPro. In SuperSpeed USB's case this is exacerbated by the fact that there are additional specifications that layer on top of SuperSpeed USB including the PIPE and xHCI interfaces. Such a profusion of layered specifications requires IP vendors to think very carefully before initiating internal verification IP developments. Most teams Cadence is familiar with have decided to use externally supplied verification IP (VIP). This enables them to deploy all their resources to building their product.

While simple bus functional models (BFMs) have served IP developer's need in the past, the advent of 1,000+ page specifications and high speed serial protocols has driven verification requirements to dramatically expand and evolve. The great majority of teams that Cadence is familiar with have chosen to use an externally supplied verification IP (VIP) for SuperSpeed USB. This is primarily due to the cost and complexity involved in creating an internal solution. Using externally supplied VIP has the additional benefit of providing an independently created model to validate the design IP against. This is analagous to hiring an outside auditor to verify the firm's internally generated accounting records. IP design teams that use their own internal model risk missing design flaws that an independent solution would commonly identify.

Figure 1. Over 2/3 of design teams are using externally supplied SuperSpeed USB VIP

The decision to outsource the SuperSpeed USB VIP makes the VIP selection criteria critically important since VIP is not all created equal. The right VIP will contribute substantially to ensuring the verification goals are met. The wrong choice could spell delay or even project cancellation. The VIP must meet several key criteria for IP developers. There are five major themes Cadence consistently hears regarding this choice. The VIP must:

• work seamlessly within a standard verification methodology and tool flow, such as OVM
• achieve high levels of coverage with minimal effort
• work with both their own choice of testbench language as well as their end users'
• provide the automation needed to increase productivity and reduce the protocol expertise required by the design/verification team
• provide metrics to guide the verification process and to measure compliance

Over the past 8 years Cadence (and its precursor, Verisity) have honed three key technologies which are now incorporated into all Cadence VIP. The first, metric-driven verification (MDV) provides the methodological underpinnings needed to efficiently verify protocols. The primary advantages of MDV are:

1. Users take advantage of a clear roadmap for their verification
2. Managers have the metrics needed to determine whether the project is on track

Engineering managers appreciate CMS because it provides their users with a natural, direct path to applying metrics to the verification process. CMS is attractive to users since it automates verification of protocol compliance and is easy to bring up and use—it is typically fully functional in the testbench within a day or two.

The second key technology is multi-language OVM. Cadence has partnered with other EDA industry vendors to deliver the Open Verification Methodology. OVM is now a multi-language open source standard. That enables it to meet the needs of IP providers and their end users since the same methodology is consistent across multiple verification languages. Simultaneously, this best addresses the need to use the verification language(s) best suited to their job. The Cadence solution provides users the freedom to select from either or both of SytemVerilog and e. Furthermore, all Cadence VIP is OVM compliant thus ensuring that it plugs and plays and is easily reused.

SuperSpeed design IP teams need to carefully weigh their choices to optimize for timeliness and quality. This means weighing the make versus buy decision, the ability to select their testbench language, and the overarching verification methodologies that will be applied. Cadence provides users the options and the automation so they can focus on the task of verifying their design. Cadence VIP provides the depth and automation needed to ensure that users can determine exactly how compliant their design is and, more importantly, how much more effort must be applied to achieve the verification goals.

• Click to explore the Cadence SuperSpeed USB VIP
• Click to explore the Cadence VIP Portfolio

About the Author

Pete Heller is Senior Product Line Manager for Verification IP (VIP) at Cadence. He has been in EDA marketing for over 10 years. He began marketing VIP at Verisity and now manages several protocols within Cadence's VIP portfolio including USB, AMBA, OCP and Ethernet. He provided the leadership behind Cadence's unique compliance Management System. Mr. Heller holds a BA in Computer Science from Indiana University as well as an MBA from Indiana University's Kelley Graduate School of Business.