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Chip planning paves way to IC success

By Richard Goering
Cadence

Depictions of the IC design flow often miss a critical step – pre-RTL chip planning and specification-level analysis. All IC design teams actually perform this function, but it’s usually an ad-hoc exercise with Excel spreadsheets. An automated chip planning tool that can leverage updated silicon IP and process information will provide much more realistic estimates of die size, power, and cost.

The term “chip planning” lacks a consistent definition. Adam Traidman, general manager of chip planning solutions at Cadence -- and former CEO of Chip Estimate Corp. before its acquisition by Cadence -- defines it as “pre-RTL what-if analysis that looks at the interrelationships between various architectural options, and their impact on size, power, and cost of the chip.” A chip planning tool provides a “sandbox” in which designers can make architectural tradeoffs, effectively optimizing the design specification to produce the smallest, fastest, cheapest chip, Traidman said.

“We use chip planning to model features for future products,” said James Goel, senior director of video engineering at Integrated Device Technology (IDT). “We want to perform economic analysis to trade-off different features and figure out what the best feature mix will be.”

Chip planning should be distinguished from “floorplanning” or “silicon virtual prototyping.” These kinds of tools generally have placement and routing algorithms, and are typically used by back-end designers to do an initial check on physical implementation. They provide netlist-level physical prototyping. It’s an important function, but very different from chip planning, which may do an initial “seed” floorplan but stays at the pre-RTL or specification level.

Chip planning is especially helpful if there’s an interface to a digital IC implementation system, including netlist-level floorplanning. For example, a chip planning tool could provide an initial floorplan, constraints, and power intent as a starting point for implementation. If information from the implementation system can be back-annotated to the chip planning tool, the tool could quickly evaluate the impact of changing specifications.

Why not just use a spreadsheet for chip planning? Excel spreadsheets aren’t connected to a database of commercial IP components, and they don’t provide estimations specific to major foundry processes. They don’t allow rapid what-if architectural analyses that could show, for example, how increased power consumption will affect cost. Spreadsheets are based on assumptions, not up-to-the-minute data. A design team might assume that a die size will be 10mm², never realizing that a chip could actually be implemented in 9mm² in a given process with a particular set of IP.

Why is up-front chip planning so important? Before he started ChipEstimate.com, Traidman had some direct personal experience as a designer that demonstrated the need for this capability.

Traidman was part of a team working on a 90 nm storage area networking chip. It couldn’t meet timing on a PCIx interface during synthesis. The company then purchased some high-speed libraries. When the design was re-synthesized, it met timing, and everyone celebrated.

Later on, back-end designers discovered that device power had significantly increased because of the high-speed libraries. The power went up around 4W, which made it impossible to use plastic ceramic packages and increased the package cost by 2 to 3 times. When a competitor started selling a comparable chip for less than it cost Traidman’s company to develop their SAN chip, the project was killed and the company lost $20 to $30 million.

Had a tool such as the Cadence® InCyte Chip Estimator been available, Traidman noted, the company could have seen the power and cost impact of switching to high-speed libraries “literally in about five seconds.” That kind of early visibility greatly helps reduce risk, he noted.

InCyte Chip Estimator is a pre-RTL chip planning tool that provides the following estimations:

• Die size. The estimation takes into account clock trees, test structures, and memory halos; calculates required power and ground I/Os; and generates a size-accurate area-based floorplan.
• Dynamic and static power. The tool models power across various chip modes, such as “standby” and “talk.” It reports active and static power for each IP, memory and block; provides a full-chip analysis; and issues reports and statistics for each operating mode. To connect to downstream implementation tools, it automatically generates Common Power Format (CPF) files.
• Performance achievability. Rather than specifying a performance level, InCyte Chip Estimator evaluates whether or not a particular timing target can be met.
• Production chip cost. This estimate includes a yield analysis and die cost calculation, package recommendations and pricing, test and assembly cost estimation, and industry wafer pricing and defect data. A lifecycle analysis forecasts chip cost over time as wafer prices and other factors change.

InCyte Chip Estimator also produces a block diagram showing architectural design intent and connectivity, and an early floorplan that helps design teams visualize physical design intent. After the floorplan is automatically generated, users can rotate or move items to avoid potential bottlenecks. The floorplan can provide a “seed” for back-end teams. “We provide the front-end designer with a really simple way to input physical information they have locked into their heads, without having to understand floorplanning tools or even have a netlist,” Traidman said.

The accuracy of the estimates depends on the level of detail that users provide. With a reasonable level of detail and calibration, die size correlates to within 95 percent of silicon in most cases, and to within 90 percent in nearly all cases (Figure 1). For 90 percent of designs, power data correlation is to within 70 percent accuracy. Users can start at a very high level of abstraction and then input more information, and thus obtain more accuracy, as the design develops.

Figure 1 – InCyte Chip Estimator die area correlation shows 95% accuracy for 70% of designs, and over 90% accuracy for 93% of designs.

A benchmark run by engineers at Cisco, and reported in Chip Design Magazine, compared two completed ASIC designs to pre-RTL InCyte die size estimates. For one ASIC, the InCyte estimate was 6.7% larger than the actual silicon, and for another, the InCyte estimate was 7.2% larger. The goal of achieving 90% accuracy with respect to silicon was achieved.

InCyte Chip Estimator is connected to an online database of more than 7,000 analog, mixed-signal and digital IP components from nearly 200 suppliers. The database also includes TSMC and Common Platform IP. Technology data is provided from leading foundries including TSMC, UMC, IBM, and Chartered.

The InCyte Chip Estimator is a client/server product. The server, which contains the IP database and foundry process data, is located at Cadence. The tool is aimed at fabless companies with customer owned tooling (COT) layout flows.

The Cadence Chip Planning System provides the same estimation technology along with an in-house server. It’s an enterprise-level product aimed at large companies who have their own internal IP and/or foundry. An IP Modeler characterizes cell libraries and processes, and creates macromodels that are used as the foundation for chip estimation. Process-specific design kits provide standard cells, I/O libraries and design rules.

Users of either tool first capture their design specifications, including blocks, gate counts, and clock speeds. They select a technology node and process, and choose IP, memories, and I/O options. Then they run estimations and visualize the results. By obtaining results within seconds, users can run rapid what-if analyses, compare different design scenarios, and evaluate their impacts on die size, power, performance, and chip cost.

Figure 2 – Cadence chip planning tools base their estimations on design specifications, IP catalog data, and technology models.

As previously noted, chip planning is most valuable when it’s linked to IC implementation. In June 2009 Cadence announced an interface between InCyte Chip Estimator and the Cadence Encounter® Digital Implementation System. The interface was demonstrated at the July 2009 Design Automation Conference.

InCyte Chip Estimator and the Chip Planning System can send information to the Encounter platform such as Verilog for connectivity, floorplans, constraints, power intent in CPF, and IP-XACT for IP metadata. These are all automatically created from the specification. The intent is to give Encounter Digital Implementation System users a starting point for Encounter RTL Compiler synthesis, as well as floorplanning, placement and routing.

The new interface will also allow the Encounter Digital Implementation System to back-annotate XML implementation data to InCyte Chip Estimator or Chip Planning System, making it possible to track and monitor the design implementation compared to the original specification. If the power consumption changes, for example, users can immediately see the impact on die size, performance, and cost. The idea is much the same as the “plan-to-closure” verification methodology provided by Cadence, in which an executable verification plan (vPlan) is continually updated as coverage metrics are obtained.

Figure 3 – Cadence chip planning solutions will provide a two-way interface to the Encounter Digital Implementation System.

At IDT, Goel uses the InCyte Chip Estimator at the initial stage of product planning for the company’s video processing chips. “It allows us to model a whole bunch of different economic scenarios and compare different scenarios,” he said. “That would be much more cumbersome in a traditional spreadsheet approach. Also, a lot of the IP we want to use is already in the database, and that makes it a lot easier to compare different product scenarios.”

To use InCyte Chip Estimator, Goel provides information about chip structure, soft IP cores, hard IP cores, macros, and I/Os. To find IP, he goes to the ChipEstimate.com web site, and Cadence then contacts the third-party IP provider to provide a detailed library. A technology browser brings in foundry process information.

Goel said the tool provides a floorplan and reports usage of gates, IP macros, and I/Os, thus showing whether an IC is core-bound or I/O-bound. Goel has not yet looked at power estimates. While the ChipEstimate.com team has “done a very good job of IP selection,” Goel said that he would like to see a broader selection of package suppliers.

To get accurate die size estimates, Goel calibrated the tool using a known-good die. Specifically, he adjusted the density parameter that specifies the utilization of logic cells. Once this was done, die size estimates were “perfectly right on.” Calibration to a given design style is important, Goel noted. “The consumer electronics chips I’m designing are going to be very different from a base station or a graphics processor.”

“It’s a good tool,” Goel concluded. “We’re using it. We’re feeding back bugs and problems, and the [Cadence] team is very responsive. I think this is definitely a growth area for Cadence.”

About the Author

Author Bio: Richard Goering has been reporting about EDA and IC design since 1985, and has worked for publications including Computer Design, EE Times and SCDsource. He joined Cadence Design Systems in March 2009 as senior manager of technical communications, and he manages the Industry Insights blog.