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Enabling Multiple Time Programmable Non-Volatile Memory for Security Applications

Craig Zajac
Virage Logic

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The need to protect critical data, be it multimedia content, personal financial or medical information, or corporate and military secrets, will continue to rise for the foreseeable future. Today’s electronic systems require a solution that can be mated with existing solutions in a flexible and cost-effective manner. Reprogrammable non-volatile memory is quickly becoming a required function in Trusted Computing, AES/DES encryption, HDMI/HDCP, and mil/aero applications. There are a number of technologies available to system designers today that address the needs of security applications.

For advanced process nodes, CMOS-based Multiple Time Programmable (MTP) and Few Time Programmable (FTP) NVM are the only solutions that meet the technology, flexibility, and security requirements as shown in the table below.

Virage Logic’s CMOS-based MTP and FTP NVM enables Flash-like performance in advanced process nodes. Using only the standard CMOS process with no additional mask layers or processing steps, the AEON® and NOVeA® product lines support true multiple time programmable non-volatile memory. These products have a long history of pushing state-of-the-art in the NVM industry, including a number of technical and reliability firsts, such as:

- First CMOS-based MTP qualified in 90nm and 65nm

- First CMOS-based MTP qualified to automotive grade standards (AEC-Q100)

- 1M write cycle endurance demonstrated at high temperature down to 90nm

- Only MTP available in Trusted Foundry Process for mil/aero applications

Because security applications span a broad range of end products, it is critical to have an NVM technology that can be customized and optimized to meet different performance targets. The floating gate technology used for CMOS-based MTP meets that requirement. As can be seen in the image below, the AEON product line has been optimized for high-performance / endurance applications using the AEON/MTP EEPROM architecture, low-power wireless applications using the AEON/MTP RFID architecture, and smallest area with the AEON/FTP Trim architecture. Combined with Virage Logic’s broad process node support, CMOS-based MTP can be implemented in a wide range of SoCs.

Figure 1

Security

Because NVM is often used to store critical encryption and security information, tamper resistance is a critical attribute. Virage Logic’s CMOS-based NVM portfolio is architected to be tamper resistant to both physical and electrical failure analysis techniques.

While traditional fuse and OTP technologies are difficult to reverse engineer, their weakness lies in the fact that the programming mechanism does permanent physical damage to the silicon structure. CMOS-based MTP on the other hand, uses a floating gate technology that makes no physical change to the silicon structures and is impossible to reverse engineer by physical inspection.

Much has been made of the potential to electrically read the data from a floating gate structure using voltage contrast. The biggest challenges to discovering the NVM contents are not disturbing the data during deprocessing (eliminating the ability to do any plasma etching), and to read the data accurately on the first try. All the common methods to determine the charge on a floating gate erase the data during the measurement. A significant amount of effort has been put into developing the capabilities to identify a leaky or defective gate in a design. Although the original intent was to identify unintended defects in the process, the same techniques can be used to segment out programmed and un-programmed antifuse structures.

In addition, the differential bitcell used in Virage Logic’s portfolio consumes exactly the same amount of current through the supply, independent of the data pattern being written or read. No matter how closely the power supply is monitored, the content of the data cannot be extracted, eliminating another common attack method.

Quality Level / Reliability

Reliability is built into Virage Logic’s architecture and testing methodology enabling CMOS-based embedded MTP that meets the exacting standards of automotive and military applications.

The main architectural advantage is that Virage Logic uses a full differential bitcell. This built-in redundancy requires that two floating gates fail in the same bit in order to have an actual data failure. There are two floating gates per bit. The data state is determined by comparing the relative charge on the two floating gates. The bitcell is designed so that the differential pair straddles the charge neutral point, and any defect will cause the floating gate to leak to the middle and stop. As shown in the figure below, this allows the MTP to read properly even when one of the floating gates has completely lost all charge.

Figure 2

The second architectural advantage is the integration of error correction. Virage Logic implements the parity bits that are required to support a single bit correct / dual bit detect error correction scheme. For example, on a 32-bit word there are 39 physical bits in the array, including the parity. Error correction further enhances the statistical reliability by requiring two bits (four total floating gates) in a word to fail before a data error occurs.

The combination of a differential bitcell and error correction allows the MTP array to tolerate significantly higher floating gate failure rates than traditional technologies. The figure below demonstrates that for the target bit counts, using a differential bitcell with integrated error correction enables Virage Logic’s CMOS-based MTP to reach automotive level quality and reliability.

Figure 3

On top of the architectural enhancements, Virage Logic’s products perform full silicon characterization and qualification testing that meets or exceeds the applicable industry standard (JEDEC or TSMC’s IP9000 for commercial / industrial applications and AEC-Q100 for automotive applications). The testing procedure has been vetted and approved by leading IC manufacturers in the consumer, automotive, and mil/aero markets.

Overall Performance Requirements

For today’s security applications, the typical NVM specification features and benefits are:

· Compatible with CMOS processing for improved cost structure

· Reprogrammable to up to 1M cycles to allow both proactive and reactive modification of the encryption keys

· Support for advanced process nodes to allow integration into advanced SoCs

· Optimized solutions to meet a myriad of target end-markets

· Resistant to both electrical and physical reverse engineering for added security

· Fully qualified to third-party standards to ensure high yield and manufacturability in production

With over 3 billion ICs shipped to date, and qualified processes from 350nm down to 65nm (with 40nm and below coming soon), Virage Logic’s AEON and NOVeA product families are the only technologies that are able to meet all of the technical requirements of the encryption and security market.

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About the Author

Craig Zajac

As the Product Marketing Manager for Virage Logic’s Embedded Non-Volatile Memory (NVM) group, Craig Zajac is responsible for product definition, positioning, pricing, and roadmap development for the embedded NVM IP products. He joined Virage Logic as part of its successful acquisition of the Impinj IP Products group in June 2008, where he was the NVM IP Product Marketing Manager. Prior to joining Impinj, he held product manager and senior applications engineering positions at National Semiconductor, ON Semiconductor, Vivid Semiconductor, and Motorola (now Freescale). He holds BS and MS degrees from Stanford University, and a MBA from Arizona State University.