Imagination Technologies has evolved a comprehensive approach to the architecture and implementation of high performance, low power SoCs (Systems-on-Chip), developed as part of the creation of its broad range of highly complex, fully synthesisable semiconductor IP cores. This approach not only helps Imagination's licensees to reduce time to market and risk but also helps Imagination to ensure its own SoC designs -- either for customer-specific designs or test chips - achieve the highest performance and design robustness under real operating conditions.
The SoCcer project, a recent SoC development undertaken by Imagination, was born from two requirements: i) a reference test chip to demonstrate key concepts with some of our latest IP cores, and ii) a pathfinder system platform for PURE, Imagination’s CE product division.
Imagination’s IMGworks group wanted to create a reference SoC design that demonstrates to customers and partners how to integrate the IP building blocks and key architectural concepts originated to ensure that Imagination’s META processor and ENSIGMA communications IP cores work well together in a system as well as individually.
Additionally, Imagination’s PURE division, the leading manufacturer of digital radio and connected audio products (all based on Imagination’s ENSIGMA and META IP cores and using SoCs from Imagination licensees), was keen to utilise its experience to help IMGworks create a design for a next generation SoC device that would better meet the digital and connected radio market’s future needs.
The “SoCcer” device is designed to meet those requirements, addressing the range of communications, Linux-hosted embedded processing, and audio DSP functions in a single, low cost SoC.
The total timescale from design start to fully operational demonstrations was only 15 months, including three months fab cycle time, device bring-up and characterisation and full software system commissioning, together with integration of multiple RF devices with multiple radios once silicon was received from the foundry. This was to be a demanding exercise that would test the limits of the knowledge gained from more than 20 previous SoC projects within Imagination.
The SoCcer architecture builds on Imagination’s concept of heterogeneous computing, which is based on the principle that any SoC should comprise a series of co-operating processor engines, each optimised for the application domain in which it is operating. For SoCcer, that meant that two highly specialised VLIW communications engines were combined with one multi-threaded 32-bit processor that handled both the general-purpose Linux-based processing as well as highly optimised audio DSP tasks. Each of these application domains requires a different software environment, yet all these software and hardware domains must work efficiently together to make a total solution.
After initial testing when the chip returned from fab, one of the first elements to be brought up was the Linux OS kernel. It was a major milestone that within one week of receiving first silicon, the chip was successfully booting Linux and running test applications, even though this was the first time Imagination had implemented in silicon its second-generation high performance META HTP processor core.
Since the device was designed to full production quality standards, it was important to use a mainstream 65nm low power process where sufficient external IP was available to meet the needs of a highly integrated system, including: high speed ADCs and DACs for IF interfacing; flexible high performance memory compilers; suitable I/Os for high speed, low power operation; and PLLs for on-chip clock generation and synchronisation.
Sourcing the additional IP blocks for the specific target process and foundry that delivered the required performance and low power specifications proved almost as challenging as the SoC design itself. Different IP was available for different processes, but often IP vendors had off-the-shelf solutions that never quite met all the specifications required, or targeted different processes. Also, it was important to be right first time in order to meet tough timescale constraints for demonstrations at major trade shows and at key customers.
Fortunately, the IMGworks team identified one vendor of ADCs and DACs that was willing to adapt their designs to Imagination’s exact specifications and process in the available timescales. Other IP blocks were sourced from proven partners who had worked with Imagination in the past with good records of success. This exercise demonstrated the challenges of acquiring process-specific IP, and the importance of having a close working relationship with the IP supplier for anything process node dependent.
Another major challenge was the design of the underlying SoC system bus infrastructure to be used. Imagination’s internal design practice is that everything is designed to be reused; so not only was a new solution designed, but compilers and tools also developed to abstract it for future SoC designs, that could take into account not just the aggregate, average and peak data bandwidth requirements, but also the likely burst traffic scenarios expected in the SoC under real operating conditions.
SoCcer’s communications capabilities, a key feature of the device, were built on its dual ENSIGMA UCCP310 multi-standard communications cores. These devices give Imagination the ability to demonstrate the new third generation UCCP310 communications engines which can now transmit as well as receive for standards like 802.11 Wi-Fi, so that a wide range of bidirectional communications can be implemented as well as broadcast receivers such as ATSC, ISDB-T, DVB-T, DAB and FM. To do this, the VLIW-like complex vector processor architecture was complemented with additional dataflow engines to enable data to flow in both directions.
SoCcer enabled Imagination to demonstrate for the first time the benefits of having multiple tuners on the same SoC – for example a reconfigurable combination of Wi-Fi communications and TV receivers at the same time.
The SoCcer project brought together one of the largest multi-disciplinary teams at Imagination, and resulted in major steps forward in the ability for Imagination to promote its total systems concepts as well as some of its latest IP cores.
Was it worthwhile? Yes – after all nothing in the realm of simulation compares to engineers seeing real silicon executing key high performance functions in real time, especially when it comes to functions like Wi-Fi or ATSC, or running the latest version of Linux and native audio DSP at the same time in a hardware multi-threaded environment.
Mark Dunn, along with Martin Ashton, was responsible for designing the first generation of POWERVR graphics products. He has a masters degree in microelectronics and is a chartered engineer. Mark now runs IMGworks.