The efficiency and performance of system interconnect fabric within ARM® processor-based Systems-on-Chip (SoC) designs, specifically paths from processor to memory have always been a critical element of any new design. It is fundamentally important that the transfer of data around the hardware system is 100 percent functional in order that the silicon is “right first time.” When the AHB™ specification was added as a part of the AMBA® 2 protocol in the early part of this century, it was essential that the above system fabric components were fully functionally verified, even though the design complexity was not at an extreme level. The continued demands for designers to deliver more SoC complexity and more performance especially in multi-media devices, has led to the AMBA specification being updated, firstly with the AMBA 3 AXI protocol and more recently with AMBA 4 AXI4 specification.
Not only do system masters now have higher throughput and lower latency demands, but designs generally include a multitude of high bandwidth intelligent processing systems for graphics and communications. Each of these systems adds architectural demands on the fabric and hence architecting solutions which can deliver on performance and low power yet be easy to verify and implement, has become a massive challenge.
Two key areas need to be addressed if the needs of system designers are to be met, firstly architectural exploration needs to be addressed providing tools to the system architects to allow performance and implementation trade-offs to be explored early in the design process enabling the correct architecture to be selected up front. Secondly, the verification of the fabric needs to become more automated in order to shorten the time to first silicon.
This article describes how Cadence and ARM have teamed up to address these challenges and ensure designers have the right tools and flows in order that they can easily architect the complex products currently planned.
Early Exploration of System Interconnect Fabric Parameters
The vastly varying demands of differing SoC designs mandate automation tools for generating today’s system interconnect fabric as there are so many capabilities needed to satisfy them. This complexity explosion is a consequence of conflicting power, performance and area (PPA) considerations when architecting an SoC. In fact modern SoCs are often composed of a number of sub-systems which only a few years ago would be considered complex systems in their own right. The component subsystems may themselves have a range of PPA constraints as well as needing to support a plethora of protocols usually including one or more of the protocols defined in the AMBA specification.
The CoreLink AMBA Designer™ product (ADR-301) from ARM is a tool architected to help solve the problem of rapidly generating a configuration of CoreLink™ system IP such as a network interconnect (NIC-301) or a dynamic memory controller (e.g. DMC-342). AMBA Designer is a GUI based tool for configuring the design time parameters used to optimize these system components. As system IP components grow in capability and complexity the value of such configuration tools is expanded, however the challenge facing system architects is to gain an understanding of the implications that the different configuration options have for PPA. The power available to rapidly configure and generate these significant IPs needs to be harnessed to exploration tools in order to better manage the consequences for PPA to ensure the system is architected “fit for purpose” from the outset.
The Cadence Chip Planning System is a product which allows exploration of system design choices at the earliest possible opportunity. The tool enables architects to do “what if” exploration of IP choices and see a rough estimation of the area and power implications of their design decisions. Estimates are based on refined physical models which provide acceptable accuracy for high level architectural and physical tradeoffs. Figure 1 shows the Chip Planning System GUI.
Figure 1: Chip Planning System GUI
The GUI enables architects to drag and drop IP, effectively creating a bill of materials for a future SoC. For more details see www.chipestimate.com. The Chip Planning System can provide approximate area and power estimates for a variety of fixed configurations of fabric but as we have discussed already the number of configuration features and the variety of protocols, bus widths and transaction pipeline depths mean that there is a huge variability in the area and power consumption of the resulting generated IP.
In order that a more accurate estimate is possible it is necessary to run through a trial synthesis of the fabric RTL. Cadence and ARM are currently working together to explore how AMBA Designer, Chip Planning System and RTL Compiler can work together in order to enable this second order area and power estimation.
So far we have mentioned power and area estimation, but not performance. On the performance front Cadence and ARM have already shown interoperability of the ARM VPE-301 product for AMBA AXI performance analysis and using it in conjunction with the Cadence Verification IP Portfolio (VIPP). This combined capability was first demonstrated live at last year’s ARM TechCon3.
Cadence is the world leader in advanced verification IP covering a huge range of protocols. Cadence has verification support for all of the AMBA protocols from the beginning of AMBA 2 up to the recently announced AMBA 4 protocol. The combination of the two technologies ensures that any realistic AMBA interconnect traffic scenario can be generated and the bandwidth and latency performance details captured and analyzed using the ARM VPE-301 analysis GUI.
In the advanced multi-media era, it is of vital importance that the memory system of a complex SoC is architected to fit the purpose for which the system is intended. The ARM VPE-301 tools allow detailed analysis of cycle-accurate data, and the constrained random nature of the Cadence AMBA VIP ensures that tests can be created which cover the whole range of system scenarios, the VPE-301 analysis tools ensure the user can check the performance levels achieved meet the system specifications.
Figure 2: Fabric Verification Automation
Automating the Verification of the Generated System Interconnect Fabric
So far we have discussed the need for exploration capabilities to help optimize the system interconnect fabric “up front”, in reality the system teams will continue to refine these design-time configuration options throughout the SoC development process to ensure the system meets its efficiency and performance objectives. This however creates a further problem, that of verification. Given the fabric may change many times throughout the lifetime of the SoC development the verification of the fabric becomes a moving target.
In order to provide an enhanced solution Cadence is working with ARM to automate the verification of the fabric generated by AMBA Designer. Figure 2 on the previous page gives a high-level outline of the flow from Chip Planning System where configuration parameters are chosen, these in turn are fed in to AMBA Designer which generates a system representation in IP-XACT format alongside the generated RTL. From this configuration the flow proceeds with the automatic generation of an OVM (soon to be UVM) testbench which configures the necessary AMBA VIP in order to drive traffic through the fabric which in turn ensures the design is verified completely.
The Cadence Compliance Management Suite (CMS) ensures that all of the potential combinations of AMBA traffic are generated to ensure complete protocol compliance is readily achieved and the results annotated onto a verification plan.
The power of this automation really comes to the fore when late system design changes are made perhaps as a consequence of the performance analysis using VPE-301 as described in the previous section. Simply re-running the flow to generate the testbenches and then launching the automatically generated regression scripts will provide coverage closure and peace of mind for system sign-off. The fabric is such a crucial component of the system it is essential that the SoC sign-off team have high confidence that all scenarios have been explored and checked ensuring data integrity and that the system memory map and Fabric topology is fully maintained in all cases.
In the ever increasingly complex world of SoC system architecture, it is essential to have powerful tools to enable flexibility in the fabric choices to ensure design decisions made early in the project are explored in order to meet PPA goals. However decisions made early in the project must not be irreversible otherwise knowledge uncovered during SoC development cannot be successfully applied and a new course plotted. Through the collaboration of ARM and Cadence idealized solutions are being developed and flows automated in order to meet the diverse complex fabric challenges as well as satisfying the need for the best time-to-market.
Nick Heaton, Senior Solutions Architect, Front-End Solutions RND, is an ASIC and EDA veteran with more than 25 years experience in design and verification of complex SoCs. Nick graduated from Brunel University, London in 1983 with First Class Honours in Engineering and Management Systems initially working as an ASIC designer for ICL after which he founded specialist ASIC Design and Verification Company Excel Consultants in 1993 servicing customers such as ARM and Altera. In 2002 Nick joined Verisity as Manager of Northern European Consulting Engineering. Nick currently works in Cadence Research and Development as a Senior Solution Architect with special responsibility for the Verification Kit, a complex and realistic golden example of verification methodologies and technologies across all of Cadences front-end products.