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IBM Cu-32 Custom Logic - Increases Memory Capacity and Processing Speeds

Gorden Starkey
IBM SRDC SOI Business Development

Explore SOI IP Here.

In October, at ARM’s Technology Conference, IBM announced a new chip-making technology designed to create advanced semiconductors that can keep pace with the exploding number of internet-connected devices and the tidal wave of data they generate. The new Cu-32 Custom Logic offering employs unique IBM technology -- designed by IBM Research -- to dramatically increase the memory capacity and processing speeds of chips used in fiber-optic and wireless networks, and in such gear as routers and switches. The technology can help manufacturers and network operators handle the data deluge driven by consumers' appetites for smart phones and other Web-connected devices. What better place to announce this remarkable technology than at the premier conference focused on designers and integrators of ARM technology? On day one of the conference, chip designers learned first hand about the benefits of manufacturing their ARM based circuitry using IBM’s new CU-32 process technology.

Silicon-on-insulator Process

IBM's silicon-on-insulator (SOI) process helps improve energy efficiency in chips using Cu-32. Since its invention by IBM in 1998, more than 100 million SOI chips have been shipped, powering the newest generation of video games and enabling a wide range of enhanced communications applications. IBM's high-k metal gate (HKMG) SOI technology can provide a wide range of benefits over bulk technology allowing chips built with the Cu-32 process to address an ever wider range of devices and applications.

Figure 1

SOI Benefits

SOI’s features include: decreased junction capacitance which results in lower active power; as much as a 30% performance improvement ,if you need it, or depending on the circuit and the application requirements you can turn that performance improvement into smaller circuits – a potential 25% reduction in circuit area is possible. Alternately, you can keep the performance constant and reduce the leakage-- 5-7X reduction is possible. You can also drop your supply voltage for some real power improvement – there is potential for as much as 40% improvement provided your circuits are still functional.

Lower power SOI circuits can translate into cost savings advantages including: lower packaging costs, lower system cooling cost and power supply cost. In addition, SOI has less susceptibility to soft errors – a 5-7x improvement over bulk, provides excellent isolation for analog circuit design and is an excellent starting material for RF applications.

Figure 2

Cu-32 Design Kit Technical Specifications

Cu-32 Custom Logic design system enables smarter silicon solutions with a complete design kit for the most demanding applications.

• Standard cell library developed by ARM
• eDRAM – High performance, low power, high density with 3000 configurations
• HSS cores supporting fiber channel standards, PCI-Express Gen1, Gen2, Gen3 standards
• IBM design methodology supporting industry standard EDA tools.

eDRAM

IBM, as the first provider of eDRAM technology in a custom-logic design system continues to expand its eDRAM offering with a compiler that can create more than 3,000 configurations. This flexibility enables smarter silicon solutions with memory optimized for a wide range of applications from high-end servers and networking applications to game processors.

• IBM's eDRAM offering features the fastest and densest eDRAM memory in the industry, achieving up to 600 MHz of random cycle performance while using up to ten times less standby power than conventional SRAM.
• IBM's trench-based eDRAM technology is optimized to deliver high performance and low power, while avoiding many of the process complexities of alternative MIM-cap-based eDRAM cells.

Figure 3

High Speed Serial Cores

Cu-32 offers the industry's first set of High Speed Serial (HSS) cores in 32nm SOI technology. IBM's HSS cores were developed to provide industry-leading jitter performance and equalization support for enhanced system performance with the lowest possible bit error ratio.

• 15G Backplane core supporting 16G Fibre Channel standard
• 15G Chip-to-Chip core supporting low-power optical and chip-to-chip applications
• 28G Backplane core supporting 32G Fibre Channel standard
• 6G standards core supporting PCI-Express Gen1 & Gen2 standards
• PCI-Express Gen3 core supporting PCI-Express Gen1, Gen2, and Gen3 standards

Design kits for standard cell libraries, memory compilers, eDRAM and supporting Fibre Channel HSS standards are available now with additional HSS standards availabilities slated forend of 2010.

Explore SOI IP Here.

• EDRAMT - 2 Port eDRAM 45nm/IBM/SOI12S0
• High Speed SerDes (HSS) - 12G BP 45nm/IBM/SOI12S0
• High Speed SerDes - 3 to 6G Stds (C4) 45nm/IBM/SOI12S0

About Gorden Starkey

Gorden Starkey is a Business Development Manager at IBM with 30+ years of experience in the semiconductor industry. Gorden's current business focus is developing new markets and generating client interest in SOI technology.