Fully Synthesizable ADC Soft IP Cores Aid Digital Design Teams for FPGAs and ASICs Allan Chin and Luciano Zoso Stellamar

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“With the explosion of programmable digital devices, and the cost and design time pressures on ASICs, isn’t it time for different ADC solution to support these new business models of rapid, optimized development that is more cost effective?”

Engineers today are challenged with cramming more functions into a smaller space, while consuming less power, and doing this all in much shorter design cycles. SoC complexity creates massive tradeoffs between size, power, time and cost. Many of these tradeoffs occur because efficient and effective analog design can be a significant roadblock to hitting deadlines on a budget. For most applications requiring analog to digital converters, 3 choices exist:

• 1. Use external ADC
• 2. Custom develop optimized analog ADC
• 3. Select hard analog ADC IP

External parts may be suitable, and cost effective for low volumes, but do not support high reliability, or low power portable devices well. Externals also represent a perpetual cost over the life of your product. Custom development may not be an option either for obvious cost and resource problems. 3rd party Analog ADC IP can support your timeline, but because of the significant development times, this route can be costly and usually target the highest performance, which may be overkill for your application. What do you do if you want to port your design to a new foundry, or process technology in the future? Additionally, your team may or may not have adequate resources to verify and test that analog IP with your system. Digital design, synthesis and testing are much easier, in general. Finally, can you use analog ADC IP with an FPGA based design? No.

With the explosion of programmable digital devices, and the cost and design time pressures on ASICs, isn’t it time for different ADC solution to support these new business models of rapid, optimized development that is more cost effective?

An A2D without the A

The concept of a “Digital ADC” has been debated for several years, with several theoretical papers hypothesizing feasibility, but showing very limited, untested performance. Stellamar can deliver a Fully Synthesizable, “Digital ADC” requiring no analog block components, and fully embeddable in the digital fabric of an ASIC or FPGA. For sensor and audio type bandwidths, this solution can enable your team to reap all the benefits that digital design has over analog design to realize:

• 50% lower power on average
• 68% smaller area on average
• Process technology independence
• Reduced risk, and cycle time
• Digital integration and synthesis
• Radiation hardened design

Through proprietary techniques, resolutions up to 14 bits are realized, and bandwidths up to 100kHz are realized depending on selected resolution. This excellent performance also comes at very low clock rates: 10-50mHz depending on parameters. This combination creates a true low power solution covering most sensor, and host of other applications:

• Sensors: temperature, pressure, voltage, current, acceleration
• Touch screen
• Voice and high quality voice
• Wireless headsets
• Hearing aids
• Medical devices
• Motor control
• Radiation hard aerospace needs
• Some optical networking modulation

Radiation Hardening

Since the design of rad hard ADCs is extremely difficult, expensive and lengthy (typically over two years), only a few rad hard ADCs are developed, and they target applications requiring the highest conversion speed. The same ADCs are then used for lower speed applications such as voltage measurements and pressure/ acceleration sensors on the system. This means that power is being wasted, and system performance is not optimized. Radiation hard applications can see significant benefit from a “Digital ADC.” Because of its digital nature, this solution can be incorporated into a rad hard ASIC process or rad hard/tolerant FPGA. Expensive, un-optimized rad hard ADCs and additional analog components such as mux and level shifter are not needed. This increases reliability and decreases power consumption and board space.

Fully Synthesizable “Digital ADC” Interface*

*This very basic block diagram is only meant to illustrate the concept of a “fully synthesizable ADC,” and is in no way meant to be a representation of the entirety of the solution.

With the “Digital” approach, a designer does not have to use external ADCs, which can take up critical board space. The ADC is right on the digital fabric, and is much easier to implement. The “Digital ADC” only uses 2 pins and a couple discrete components depicted in the diagram. Now your team has an ADC embedded in the digital fabric of your ASIC or FPGA, which is properly optimized for your application, and you have also reduced board space, complexity and testing time, while increasing MTBF. This approach is much easier to implement and test which can greatly enhance your ability to meet time to market.

For additional ADC functionality in the conventional approaches, either more ADC chips would be added, or an analog multiplexer would have to be added. With the “Digital ADC” solution, a designer could just add more “Digital ADC” IP blocks to take advantage of the size and power savings.

The following are typical frequency response plots for a “Digital ADC” with a bandwidth of 20 kHz. The plots show an output with two different amplitudes of a 15 kHz input frequency. The first has amplitude of 1.8 V_pp while the second is 60 dB lower with amplitude of 1.8 mV_pp.

Figure 1: Input frequency 15 kHz, input amplitude 1.8 Vpp

Figure 2: Input frequency 15 kHz, input amplitude 1.8 mV_pp

The power estimate for a Xilinx Spartan 3AN which contains a single channel, 12 bit, 20 kHz bandwidth “Digital ADC” with a typical digital filter, an I2S interface and a SPDIF interface is 6mW. Power will vary among FPGA vendors and FPGA families, and will depend on customer requirements.

FPGA implementation example:

Rad hard/tolerant FPGAs are becoming more common in commercial and military satellites. For system health monitoring: measuring voltage, current, temperature, pressure etc., an expensive rad hard ADC must be used. Another problem for FPGAs is that in both commercial and military applications, these ADCs are external to the digital fabric, taking up space, power and impacting reliability. These critical factors are all high on the priority list when a satellite is designed. With a “Digital ADC” designers can now use the FPGA digital fabric thus reducing board space, weight, power and increasing reliability while still providing the same functionality. The reduction of weight, power and increased reliability amounts to lowering both the cost of the satellite itself, and also the insertion costs. With increased reliability MTBF will increase, resulting in longer satellite lifetime.

ASIC implementation example:

ASIC applications with ADCs as a large part of a small and mobile system, are perfect targets for the “Digital ADC” solution. In the typical Bluetooth headset there are roughly 4 ADCs for noise cancellation and voice. These designs are driven by consumer demand for more talk time and smaller products. If “Digital ADCs” replaced the analog ADCs for noise cancellation and voice, the design could actually save at least 50% of the power used by the ADCs in the current Bluetooth implementation, while reducing the total area of all the ADCs by 68%. The result would be longer talk time and a smaller footprint with no loss in functionality or performance. The optimized “Digital ADC” can be developed in weeks, targeted to system requirements, and is fully synthesizable. Perhaps most appealing is that a “Digital ADC” is technology independent and would take full advantage of a technology shrink, while requiring no redesign. This would reduce risks and time to market, enable first pass success, and directly impact the bottom line from a cost per wafer perspective.

Deliverables

A “Digital ADC” is suitable for ASIC or FPGA applications. Current FPGA evaluation boards are available for purchase on at http://www.stellamar.com, and show 11 bits of resolution over a 5 kHz bandwidth, and 10 bits over 20 kHz bandwidth. A purchased Digital ADC IP block can be specifically optimized for your resolution and sample rate requirements. ASIC performance implementations can be improved due to better control over mixed signal rules. Stellamar works with customers to deliver customized RTL that best suits requirements. The encrypted RTL will also allow the customer to target their desired technology and foundry. Along with the RTL, Stellamar provides a detailed Implementation Guide, and offers customer support to ensure proper implementation.

Conclusion

Designers requiring ADC integration in either an FPGA or ASIC now have a simple, flexible and complete solution. With a Stellamar “Digital ADC”, most of the common bottleneck issues caused by ADC integration are removed. The result is a “Digital ADC” that can be easily embedded in any ASIC or FPGA- not just large and expensive mixed signal FPGAs. This ADC will also be much smaller and less power hungry for low power portable applications. Finally, a Digital ADC can be easily ported across process technologies without re-design to leverage the ASIC cost structure and realize bottom line savings. In the near future, engineers will be better able to integrate and synthesize other components in the analog domain. The “Digital ADC” is the first step.

About Stellamar:

Stellamar is a full service design, consulting and IP licensing firm specializing in digital and mixed signal applications, with particular deep domain expertise in creating solutions, which enable analog functions to be implemented in a digital environment.
The mission is to provide valuable IP cores and design services to conquer challenges of mixed signal design and integration. Our products and services allow engineering teams around the world to add value for their customers by focusing on what they do best. Through this mission, Stellamar drives down cost and design time for some of the most complex and demanding parts of an overall system design. The primary aim of our IP cores is to provide analog functionality with all the benefits of a digital design process: shorter design cycles, lower risk, established design and layout tools, digital test methodology and portability across process technologies.

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• 10 bit Digital ADC
• 12 bit Digital ADC
• 14 bit Digital ADC
  

  About the Author

  Allan Chin

  Allan Chin has over 30 years of design experience with high performance digital and mixed-signal systems, and holding various management positions at Motorola/Freescale, Mentor Graphics and Honeywell before founding Stellamar. His broad expertise covers many areas of IC design including system requirement definition, chip development, mixed-signal simulation, verification, prototyping, and testing.
  Allan can be reached at allan.chin@stellamar.com.

  Luciano Zoso

  Luciano Zoso is an accomplished engineer and inventor with over thirty years of experience in digital signal processing at companies such as CSELT research Center in Italy, Hayes Microcomputer and Motorola/Freescale before founding Stellamar. He has successfully applied his expertise in the areas of voice band modems, Sigma-Delta converters, multi-standard digital video encoders and decoders, stereo encoders, GPS receivers as well as sensors. His experience ranges from system level design and simulation to full implementation.
  Luciano can be reached at luciano.zoso@stellamar.com.