This year at SEMICON 2011 Taiwan, the topic of 3D IC Test had been given a half-day time in a new independent 3D IC Test Forum, separated from other topics of 3D IC technologies. Indeed, test is a very serious topic and challenges are especially daunting with 3D TSV and vertical integration. It is no longer feasible to defer test cost & test time downstream in the production chain, one bad die in a stack found in late stages of a 3D chip's production can be extremely expensive as the entire chip is considered defective - even with many other good dies. The traditionally structured - potentially avalanching - test cost may be no longer tolerable with new 3D chips.
Many insights on the challenges with testing 3D devices were presented very comprehensively by Qualcomm's presentation: Test Challenges in 3D TSV SOC. These challenges include test access, probe card pitch, wearing from probing, large number of TSV to test (for things like wide IO memory), ATE drive current / ESD issues and many more. Many the issues already exist with the present test methods - even without 3D TSV process, 3D TSV only makes many the existing test issues so much more complex and costly - without newer simpler methodology. Teradyne for example is one ATE maker already thinking ahead, by offering protocol aware ATE, the company is already prepared for smarter test methods on new chips.
Presently de facto test methods, with off-chip ATE bearing the brunt of almost all test traffics, is becoming ever costlier to catch up with advanced process nodes. Probe pitch has reach the limit, probing techniques and reliability are high challenges, test IO is limited and is expensive, and trying to catch up with performance of chip technologies is expensive for ATE. Even though in the presently test time based test cost structure, test service providers can often be very good at "cost-down" to stay competitive, the present day mainstream ATE-centric methodology is still the hard way to try and keep down test costs; and could become impractical with the coming 3D TSV.
The way to remove all the above mentioned intricacies associated with the present ATE centered mainstream testing, is just to remove the intricacies: the external off-chip test traffics that are predominantly driven by ATE. If test traffics - or at least the bulk of – can be internally on-chip instead, most the mentioned difficulties associated with the present ATE centered test methods are practically eliminated: test IO will no longer be a bottleneck; ATE are no longer required to push performance limit to match chips; probing too no longer need to push the performance, instead, reliability can be more focused on - without needing to be overly concerned about tradeoffs associated with pushing performance; everything will just be much simpler and cheaper with the external test systems. BISTV is what 3D TSV chips will need, if people are serious about keeping costs and DPM down.
Various BIST technologies have been in existence for a while, but BIST had never really become mainstream, for most the past BIST technologies are still somewhat limited in capabilities. And to truly enable fully autonomous on-chip self-testing, it is not enough to only generate test patterns on chips, test responses must also be verified, on-chip, somehow! Therefore, a Built-In Self-Test-Verification (BISTV) technology is really what is called for, to fully enable the true all-in-chip testing; thus, simplifying external off-chip test technologies and reducing costs. The de facto test time based present day test cost structure would be transformed with the new BISTV in chips, and testing can become more efficient and less complicated with the reduced requirement of performance and technological complexities from ATE and probe cards.
A practical BISTV technology based on cryptographic hash functions and the IP is already offered by YFL elite. The BISTV is suitable for testing and (virtual) self-verifying both memory and logics on-chip, fully autonomously. There is also at least one other ADC/DAC based self-test solution for analogs offered by another company. Therefore, solutions to test chips fully autonomously are already here!
3D TSV is the upcoming technology for new SOC devices offering cutting-edge advantages in density, power, and performance. But if test methodologies standstill, the potential repercussion of cost and wasting may be too severe to ignore. In chip production, the further downstream defects are detected, the higher the cost for wasted time, energy, and materials. And for 3D TSV devices, the costs literally avalanche! Deferring test time or test cost downstream may be too costly to even consider for 3D devices. That is why Qualcomm also mentioned - during the presentation at SEMICON 2011 Taiwan - the need for a KGD or PGD (Pretty Good Die) flow for 3D devices.
For example, some chips with lower margins may be more tempted to defer much test time downstream as possible. The bulk of testing - time & cost - can often be left to even the module vendors. The cost of defect at such the stage can be magnitudes higher. One defective chip in a module could mean wasting a lot of other good chips in the same module; or at least bring the value down significantly - even if some defective areas can be bypassed or turned off by software or hardware. Yield number can be misleading at times; sometimes when the yield number is high, DPM is also high.
Using less test time and applying test practice with early stage KGD/PGD flow will not only save more time, cost, and materials; it will also be a greener manufacturing practice, with less energy spent, less - often very expensive - materials wasted. 3D TSV will definitely need BISTV, but 2D chips will definitely be much more cost efficient as well with BISTV technology.
Yen Liu founded YFL Elite in 2009 and is presently CEO and Chief Design Engineer at the company. He has over ten years experience in the semiconductor industry and presently has several patents granted in areas of semiconductor testing and cryptographic security.