Much like assertions for Assertion-Based Verification (ABV), this new methodology targets the verification of analog, mixed signal and multi-domain designs by providing the means to embed so-called detectors into the design and/or test bench.
Detectors can be used early in the design process to observe automatically the circuit behavior, check whether specifications (functional, device properties) are met and reliably announce violations. They offer debugging possibilities through the option to pause or abort the simulation and also thanks to the generation of messages issued in the simulation log.
Detectors are virtual devices for on-the-fly processing during transient simulation. They are embedded into the circuit components or test bench to observe physical domain quantities, such as voltages or currents, and check whether operating or connection conditions are respected. Networks of detectors can be created by interconnecting them to perform more complex checks and detections including calculations.
2. THE DETECTOR METHODOLOGY
The vision that led to the implementation of the detector library was to improve design security and quality of analog and mixed-signal designs through automated and reliable verification and avoidance of manual waveform analysis.
Detectors are built to observe specific system characteristics, e.g. to measure currents, voltages, frequencies, delays, jitters etc., on the condition to not influence the behavior of the design under simulation. Detectors announce on-the-fly, during simulation, when signals violate specification rules and log these events in report files for further analysis. Depending on the severity level set up for the alerts, the simulation can be aborted, paused or continued for debugging purposes.
Figure 1 shows the typical detector structure, which is an assembly of fundamental elements. The core of the detector library provides the internal functions as listed below:
Probes (1) (mandatory): monitor a value, optionally a differential value (I) in the circuit and convert a physical domain flow or potential quantity to a real quantity. This quantity is the value that a checker can observe directly, or it can be an input for a calculator.
Triggers (2) (optional): used to activate a checker.
Calculators (3) (optional): used to calculate a value that must be observed but is not directly accessible in the circuit, e.g. for the electrical domain, the measurement of the power factor can be combined with the current and voltage measurement to give the instantaneous active and reactive power. The inputs are generally the outputs of probes or of other calculators.
Checkers (4) (mandatory): observe if the input quantity stays within its limits or not. A checker is enabled via a boolean "true" at the ENABLE input. If the input is out of the limits, i.e. in case of a violation, the TRIGGER will be "true". The input of a checker is generally the output of a probe or of a calculator. Checkers are generally activated by triggers or other detectors.
Messengers (5) (mandatory): announce violations to the user, on the screen and/or in a log file, when ENABLE is "true". Depending on the severity level, the simulation can be paused or aborted.
Figure 1: Typical detector structure
The above mentioned fundamental elements can be combined to build any thinkable detector. The general structure of a typical assembled detector consists of:
input value(s) (I) that are observed (monitored and converted using a probe (1)),
a trigger that enables the observation (2),
an optional calculator that calculates the value to observe out of the input value(s) (3)
a checker that checks if a specification violation occurs (4) and
a messenger that reports the violation (5)
While implementing the detectors, special focus was put on being compatible with any possible application, for instance through parameterization, in order to be adaptable to different specifications.
Figure 2: Detector featured Mixed-Signal Design and Circuit Transfer
3. DESIGN VERIFICATION PROCESS
The methodology verification flow is shown in Figure 3. The fundamental detector elements will be interconnected, graphically as blocks, depending on the specification/functionality to check. This assembled detector observes design specification violations during simulation. The detector log files can be analyzed for further investigation during debug.
Contrarily to PSL based mixed-signal verification approaches, this methodology makes use of the standard analog Hardware Description Languages (HDL) VHDL-AMS and Verilog-A(MS) to build a library of detectors. This ensures that designers using different simulators supporting multiple languages (Verilog(-A(MS)), VHDL(-AMS), SPICE...) can benefit from these developments and are not bound to special simulators or simulator couplings.
It allows monitoring online design specification violations while performing simulations of any hierarchical level (architectural, behavioral, functional and electrical).
Figure 2 illustrates the application of the detectors in circuit design, transfer and System-on-Chip (SoC) Integration.
Detectors speed up the verification process through automatic specification rule checks. The detectors replace proprietary simulator specific test bench code with independent detectors embedded in the model. Thanks to the use of standard HDL, the same detectors can operate in different simulator environments without the need to adapt the test bench, which means that the model of the Silicon IP can be delivered to a customer to check whether it behaves as expected in the customers' environment. For SoC Integration, embedded detectors enable checking that integration rules are respected, verifying that specifications are met and detecting unexpected component interactions.
The main benefit is that SoC Integrators do not have to perform manual, error prone, checking of signals to verify that specifications are met and thereby get a reliable feedback automatically during the simulation.
Figure 3: Verification flow
During system design, this methodology can also be used for equivalence checking of models at different abstraction levels. For complete SoCs, the simulation of the whole design with transistor-level models is not realistic because of the long simulation time and of the computing effort required. Therefore, transistor-level models of subsystems will be replaced by behavioral models. It has to be ensured that the replacement model is equivalent on its interface to the circuit. Figure 4 shows how detectors help to verify that both the transistor level and the behavioral model have the same "detector outputs" when the same test patterns are applied.
Figure 4: Detector-based equivalence checking
The advantage of using a library of detectors, rather than using a special language, is that already verified models can be reused and the libraries remain untouched.
4. ADVANTAGES OF METHODOLOGY
As the detectors can be integrated into schematics, this implies that the Design of Experiments based on these checkers is kept at each step of the bottom-up process: the integration of schematics at a higher hierarchical level is secured by the detectors which embed usage verification. Consequently, designers save time by not having to define again necessary consistency verifications as the design is instantiated with its embedded detector(s), as a self-controlled black-box. For analog design, if used in a schematic editor which enables selective netlisting to filter detectors for layout netlist, the same reference schematic can be used both for simulation and for layout.
As detectors are on-the-fly checkers, when an error occurs, the designer is immediately informed and can perform debug immediately. Furthermore, design robustness checks with many parameter variations can be performed in batch mode and the detectors can help identify sensitive parameters by reporting simulation runs which were out of specification.
In conclusion, it implies that detectors increase the Quality Control in a lower lead-time, and accelerate the final Time-to-Market.
5. THE DEMONSTRATOR
In design example of Figure 5, the two Analog Front-Ends (AFEs) digitize the two analog input signals (sinusoidal current and voltage waves) respectively, and then output the digitized data to the computation unit which handles the power calculation in digital manner. As this paper focuses on the verification of the analog part, Figure 5 only represents the analog part of the entire power meter design.
Figure 5 illustrates an example of the use of two kinds of detectors with their input range specifications:
D1 and D2 the same type of detectors with different parameters (0.8 Vrms maximum for differential current channel input, 0.4 Vrms maximum for single-ended voltage channel input). This shows that the same detector is adaptable to different specifications through parameterization.
D3 is the phase shifting detector which checks whether two sinusoidal waves of the current and voltage channels are in phase or not.
The main voltage and current flowing to load are measured using AFEs, which contain Analog-to-Digital Converters (ADC). Power consumed by the load is then calculated by multiplying these measured values (VrmsxIrmsxcos ?). Finally, the total active energy [Wh] can be determined by summing the power in time.
The main voltage is too large to be processed by the AFE input directly. Therefore, it has to be reduced by a certain ratio down to the specified input range of the voltage channel AFE. Similarly, the load current is converted into a voltage, by a current transformer, to have the appropriate input value according to the current channel AFE input range specification. Detectors D1 and D2 must have the ability to detect whether the input signals (differential or single-ended) are within their specified ranges during simulation.
The phase shifting between two channels has significant impact on the accuracy of the power calculation. The extra phase-shifting which can be added by the mismatch of external components must be measured to be able to compensate. Detector D3 is required to detect the phase response and report the result during or after the simulation.
It is important to mention that the two kinds of detectors, as well as the application, presented in this paper are very simple and only for illustration of the methodology.
The described test bench is shown in Figure 5. One can see the input range detectors D1 and D2, which observe the input voltages of the AFEs. Also shown is D3, which observes the phase shift between the two AFE channels (voltage and current). To have a power meter which complies with the standards, the extra phase shift must be compensated if it is higher than 0.05°, which is equivalent to a time offset of 2.778us.
Figure 6 shows the transient simulation zoomed in to show the phase difference, which is 0.144° with an equivalence time offset of 8us. The detector warning shown at the bottom pane of the simulator reliably announces that this value is above the specified level.
Figure 5: Detectors check the input range and phase shifting of a power meter design.
Figure 6: Transient simulation, zoomed in phase shift
With use of the proposed methodology, the designer is able to create and compose specification rule checkers (detectors) by using the parameterized fundamental elements. Critical design parts can be observed continuously. During simulation, the detectors reliably check whether the design operates in its specifications or not. Consequently, the verification phase can be automated to avoid error prone manual analysis of waveforms.
The compliance of the design specification, and therefore the overall functionality of a circuit, can be totally observed with dedicated detectors. This increases the comprehension of the design and of the influence of certain design parameters on the functionality of the circuit, thereby increasing design robustness. The use of detectors in simulation allows the identification of design defects early in the design process and therefore provides the means to reduce and even remove design iterations.
All these features increase designer's productivity and ensure design security through an accelerated automatic checking. Since the detectors are implemented in a standardized HDL, they guarantee the compatibility of separate application schematics with different simulators and minimize efforts in creating and embedding specification rule checks independently of the overall test bench.
Detectors offer diagnostic support in several fields, see Figure 7.
Figure 7: Detector support through the design flow
For mixed-signal circuit design, detectors are used to observe specification violations.
Multi-level model calibration and circuit optimization is supported by the detectors through using a sequencing method to adapt model parameters to converge to measurements or simulations on lower levels.
Design robustness tests can be enhanced through the use of detectors with a sequencing method to ensure that the Silicon IP stays in its specification.
Circuit transfer efforts can be reduced through providing virtual sockets with detectors on Silicon IP ports to observe if specifications are met in a changed environment independently from simulator.
Equivalence checking provides the possibility to check the equivalence between two models of the same or different levels (or languages) of abstraction while applying detectors at the model interfaces (ports).
Dirk Dammers joined Dolphin Integration in 2001 as development engineer in modeling of mechatronic systems with VHDL-AMS and authored and co-authored several publications in this field. He is product manager of the EMBLEM Detectors library.
Dirk holds a degree (Diplom Ingenieur) in electrical engineering from Gerhard Mercator University of Duisburg, Germany. Mr. Dammers can be reached at firstname.lastname@example.org