Using Cost-Effective and Secure Field-Programmable 1T-OTP to Emulate MTP Jim Lipman and Craig Downing Sidense

Applications for non-volatile memory (NVM) encompass a wide range of programming requirements. Some products require one-time programmable (OTP) memory that is programmed during chip fabrication – mask ROM is good for this purpose if the code is frozen. Other products need field-programmable OTP for applications such as analog trimming, necessitating the use of secure in-system programmable NVM.

A different class of NVM applications requires that the memory not only be field programmable, but also that it can be programmed multiple times. Some may require reprogramming just a few times; examples include updating stored code or encryption keys. On the other end of the multiple-time programmable (MTP) use spectrum is NVM that may be programmed thousands or even hundreds of thousands of times over the life of a product; for example, to store user data.

Applications that need frequent updating of memory content, such as user data and media files, need an NVM technology such as flash memory, which can be either embedded in an SoC or supplied using a dedicated external flash memory chip. However, there are many applications that currently use flash or EEPROM that can benefit by using one-transistor bit cell OTP (1T-OTP) memory instead, in an emulated MTP (eMTP) mode. These are the applications that need reprogramming just a few times over the product's lifetime, such as for HDCP encryption keys, firmware, or product IDs that track product updates.

The benefits of 1T-OTP include lower chip processing cost and smaller memory footprints. The small size of a 1T-OTP bit cell also allows it to be used for applications where a small number of bits need to be updated many thousands of times as a practical replacement for EEPROM.

When using OTP memory for eMTP applications, remember that not all OTP is created equal. For emulated MTP usage, the OTP you choose must have a set of attributes that will allow it meet the cost, technology and security constraints associated with a particular design. While the attribute set may vary from application to application, there are a few requirements that apply to most or all potential eMTP applications:

Field programmability

Multi-time programming of all or part of an embedded memory should easily be done “in the field” without special equipment, either during chip development or when the silicon is already in the final system. This can be done using an integrated charge pump with the OTP, eliminating the need for an external voltage source and an extra pad on the chip.

High density

One significant application for OTP memory in an emulated MTP mode is updating or replacing processor code during system development and throughout the lifetime of the end product. The need to update large amounts of code, often hundreds of thousands or millions of bits, dictates that the OTP be very high density. Single-transistor antifuse-based technology, such as Sidense’s 1T-Fuse^TM, enables very high density memory macros, which minimize the chip area needed for an OTP macro used to store current and future versions of code.

Low implementation cost

With most silicon development being consumer-product driven, OTP for eMTP use must be low cost, ideally adding no additional masks or process steps to the standard CMOS logic process flow. In addition, for eMTP applications requiring large amounts of storage, there should be an easy and inexpensive path to convert embedded OTP to mask ROM for code storage that has been frozen. OTP such as that from Sidense supports easy conversion of OTP to ROM, in a standard process flow, with only a single diffusion mask change.

High security

When used for eMTP applications such as code and encryption key storage, OTP must be very secure to protect the memory’s contents from theft or malicious alteration. Since traditional MTP memory technologies rely on some type of charge storage, they are susceptible to scanning and other techniques that can be used to ascertain the memory’s contents. Based on controlled oxide breakdown for bit-cell programming, antifuse-based 1T-OTP does not use charge storage and is virtually impossible to reverse engineer, making it an ideal solution for secure storage.

The following table shows OTP for several applications that can benefit by using embedded OTP in an eMTP mode.

Table 1

1T-OTP memory IP may be used for emulated eMTP operation as a very reliable, highly secure and more cost-effective alternative to embedded flash, EEPROM and eFuses. Sidense’s 1T-Fuse^TM single-transistor bit cell enables very high density OTP macros, making the OTP well suited for applications where data will be reprogrammed once or several times, while minimizing die area and cost compared to alternative NVM solutions

The simplicity and flexibility of the OTP macro’s emulated erase operation lets you implement different re-programmability schemes within the OTP address space. Another advantage of this type of eMTP solution is a significant reduction of the traditional NVM erase time and complexity, since the erase procedure can often be replaced by a single bit write operation

A typical approach for eMTP operation is to reserve additional, un-programmed OTP space for new data and allocate some additional storage for a tag to keep track of which memory segment is currently being used. The information in the tag area is used to calculate the address offset for the data. The amount of uncommitted OTP storage depends on the number of times you want to update the stored information. For example, if you need 4 Kbits of storage that will be rewritten 7 times, you will need a 32 Kbit macro (8 x 4 Kbits), or to rewrite 64 bits up to four thousand times you will need 256 Kbits.

Sidense’s SiPROM macrocells have extra space called boot rows where you can store the tag information. Depending on the eMTP architecture you use, the tag information can be automatically read by the macrocell at power-up (boot time) for bank-based replacement, where a whole section of the address space is replaced, resulting in single-cycle random read access. Otherwise, for a word-based replacement (EEPROM emulation), it would be read for every access.

The following figure is an example of a macrocell in which some of the storage is fixed and will not be updated and other portions comprise an initially programmed eMTP block plus unused space for rewriting the eMTP block multiple times.

Figure 1

This figure shows a generic example of a possible OTP memory address space map. The memory tag area (for eMTP tracking) is located in the boot rows of sector 0. The main memory address space is allocated for eMTP data. In this example we assume that the eMTP initialization phase includes calculating and storing the eMTP address offset based on the information in the Memory Tracking Area (boot rows). All the memory access is then handled by a memory controller, which translates the external address into the OTP address space.

The next figure is an example of a 512 Byte, eight-times programmable eMTP (8xMTP) implemented with a 4Kx8 (32Kbit) SiPROM macrocell. The eMTP is auto-initialized by the macrocell at power-up time. The SiPROM memory address space is organized in one bank and 8 Sectors. Each sector contains a boot block space of 16 rows. The eMTP tag information is stored in the boot block of sector 0 (rows 0 and 2). The sector size is 4 Kbits (512x8 bits). To reprogram the storage you control the sector address according to the tag information. Since only an 8-bit tag is needed for eight-time programmability, the remaining boot rows in the sectors are available for testing, chip ID, or other OTP applications.

Figure 2

In many instances MTP operation can be accomplished using 1T-OTP memory in an eMTP mode, with the advantages of antifuse-based 1T-OTP – smaller size, lower power and higher security – over other NVM memory. In addition, with 1T-OTP you are using a memory technology that does not add process cost and can pack a very large number of bits into a small area. By using an n-times larger OTP array, you get an n-times programmable MTP memory as a superior alternative to other types of NVM. The attributes of Sidense’s 1T-OTP make it a good choice when considering using OTP operating in an eMTP mode as a replacement for larger, more expensive and less secure MTP memory.

Explore Sidense IP here

• OTP/eMTP: 128 Kbit NVM in 65nm Standard Logic CMOS process
• OTP/eMTP: Very low power 64 Kbit NVM in 180nm Standard Logic CMOS process
• OTP/eMTP: Ultra low power 2 Kbit NVM in 180nm Standard Logic CMOS process

About the Authors

Jim Lipman

Jim Lipman is Sidense's marketing director. His work experience includes positions at TechOnLine, VLSI Technology, Hewlett-Packard and Texas Instruments. Jim has a D.Eng from SMU and an MBA from Golden Gate University. He can be reached at jim@sidense.com.

Craig Downing

Craig Downing is product marketing manager at Sidense. He received a B.Eng. in electrical engineering from McGill University in Montreal. Craig can be reached at cdowning@sidense.com.