Providing Efficient Storage for Analog Mixed Signal Trimming Data David Hsu Kilopass Technology

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An increasing amount of analog and mixed signal circuits are finding their way into smart phones and tablets and providing an enhanced user experience. For example, the sensors on a smart phone that detect acceleration, proximity, and magnetic orientation, enable new features and services to the end user such as the exploding amount of location-based services coming on the market. Other analog and mixed signal circuits contributing to the user's experience include capacitive touchscreens, LCD drivers, and power management units as shown in the figure. Interfacing analog circuits to a digital system require analog-to-digital converters (ADC) and digital to analog converters (DAC) in addition to the amplifiers needed to boost the very small signals emanating from these analog circuits.

Figure One

Because the ADCs, DACs, and amplifiers are analog devices, they require trimming during manufacture to ensure that each will produce the same result from a given reference signal. In addition, all analog circuits are subject to drift over time. To compensate, the trimming values of the circuits can be adjusted to accommodate for changes in circuit operation with age: adjust amplifier gain/offset voltage, zero out a DAC or an ADC converter, etc. Several methods have been used to store these trimming values in the past including the more popular efuse and EEPROM. Both have disadvantages for this new generation of sensors that are overcome by one-time programmable, anti-fuse, nonvolatile memory (NVM).

Let's begin by describing the existing alternatives and contrast each with the preferred anti-fuse NVM. The efuse is attractive because it scales with process technology shrinks. In most cases, the efuse is supplied by the foundry at little or no cost. Having an efuse supplied by the foundry makes it difficult to move a design to another silicon supplier, to provide second source or an alternative chip supply. Efuse solutions blow the silicide on the poly line creating a change in resistance: converting a low-resistance path to an open circuit. For small capacity solutions not requiring field updates or security, it is a viable solution. For applications where an NVM is providing on-chip storage of trimming data for a number of sensors, MEMS devices, and amplifiers, the storage capacity limit of 8kb might make efuse impractical.

However, as shown in the table, efuse is at a cost disadvantage against an anti-fuse NVM solution in the case of an LCD driver. Both provide calibration and trimming in a 1Kb memory block. However, the efuse's cost per unit is 3X the cost of an anti-fuse NVM. For memory storage capacities beyond 8Kb, the efuse becomes area inefficient, since it requires duplicating another efuse block comprising control logic and memory array. By contrast, the anti-fuse NVM, which at 8Kb is already half the size of an equivalent efuse block, simply adds additional memory cells.

Figure Two

EEPROM is a better alternative to efuse if higher storage capacity and field programming is required. EEPROM is sensitive to temperature extremes and stored trim data could be lost at especially high operating temperatures. However the biggest problem for using EEPROM is the cost of integrating the memory on-chip. Adding a floating gate memory cell to a standard logic CMOS process involves as many as 15 additional mask steps. The alternative is to store the trim data off-chip but at the cost of the extra system component and the additional I/O pin required to transfer the trim data on-chip at power up.

The major advantage of anti-fuse NVM is that it is implemented in a standard logic CMOS process requiring no additional process steps nor special erase or bake requirements during test. As a general rule, the logic-flash process combination adds a 30- to 40-percent cost premium to the wafer. In addition, the availability of built-in self-test (BIST) and built-in self-repair (BISR) on an anti-fuse NVM provides for highly enhanced field programming yield, where failure cost is much higher. Furthermore, the anti-fuse NVM bit cell is a fifth to a tenth smaller in size than the EEPROM bit cell. Finally, anti-fuse NVM has an operating temperature range between -40C and 125C, thus easily handling the operating extremes of portable consumer devices. Click here for a video on anti-fuse NVM IP in analog/mixed-signal applications.

Kilopass Technology Inc. developed the first anti-fuse NVM that could be fabricated in standard logic CMOS. The company holds the original patents on this invention and today has 58 patents granted or pending. Its extra-permanent XPM^TM memory family ranges up to 1Mb. Kilopass' Gusto^TM product line is the industry's first 4Mb embedded non-volatile memory, enabling on-chip code storage in standard CMOS logic. The company's recently released Itera^TM product line provides multi-time programmable non-volatile memory with up to 1 megabit (Mb) of storage capacity and 1000 cycles of re-programmability, to serve over half of today mobile and consumer applications. All three product lines are available in standard logic CMOS processes from 180nm to 40nm at dozen of foundries and integrated device manufacturers.

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• NVM 64Kb to 1Mb TSMC 130nm
• NVM 64Kb to 1Mb SMIC 180nm
• NVM 64Kb to 1Mb Dongbu 130nm

About the Author

David Hsu
Kilopass Technology

David Hsu is the senior field marketing and applications manager at Kilopass Technology Inc. He graduated from The Ohio State University and received his Master's degree in Electrical Engineering from Purdue University. Hsu started his career in Siemens Components in the telecommunication division; later at Datapath Systems' read channel program and as principal engineer at LSI Logic HyperPHy SerDes group from 1998 to 2006. Between 2006-2009, he worked at TSMC in the role of customer support and in IP/Library quality management.