Manuel Mota — Synopsys
In modern communication systems, the drive to simplify analog processing and increase system flexibility has pushed the digital / analog boundary closer to the antenna, resulting in signals crossing this boundary at intermediate frequencies (IF). In addition, channel bandwidth is increasing beyond the 100 MHz range. In the transmit path, these trends set new requirements for digital-to-analog converter (DAC) performance, which are addressed by newly available high-speed DACs.
This article describes some of the most relevant characteristics of these modern transmit architectures for broadband communications and how the new high-speed transmit DACs are used to support their implementation.
Novel system architectures for broadband transmission
The evolution of digital signal processing (DSP) techniques, together with the ability to integrate substantial digital circuitry in modern system-on-chips (SoCs) is driving the development of novel transceiver architectures for broadband wireless and cable communications.
These architectures aim at transferring system functionality from the analog domain into the digital domain. Reducing the complexity of the analog signal processing block reduces power dissipation and area use. Furthermore, as DSP systems offer programmable blocks, more system functionality in the digital domain adds flexibility to the system.
For example, communication transceivers can be upgraded to accommodate changes to the communications protocol or can be easily reconfigured to support new ones. These features render the SoC "future proof" and more flexible. Using the reprogrammable features of DSPs, a single SoC can support different protocols in different regions through simple reconfiguration of the soft IP, thus reducing time to market.
Software defined radio (SDR) architectures ultimately eliminate all analog processing by moving the interface between analog and digital to the radio antenna, as illustrated in Figure 1. By eliminating the analog blocks, the SoC can take full advantage of area and power scaling inherent to digital implementations in deep submicron processes.
Figure 1: Conceptual block diagram of a transmitter based on an SDR architecture
The gating factor that has limited the evolution of these architectures is the analog / digital interface, and specifically the analog-to-digital converter (ADC) and the DAC. Until recently, the high speed and high performance required for these converters was not possible to implement in integrated circuits. However, these converters' technology is finally catching up, allowing system designers to implement traditionally analog functions in the digital domain.
While this article focuses on the transmit path and in the DAC, a similar trend can be identified in the receive path and in the ADC.
Traditional transmit DACs
DACs are a key element of the broadband communication transmit path. Current-steering DACs are the ideal architecture for broadband applications because they offer the best performance at the lowest power dissipation when compared to alternative DAC topologies.
In a simplified way, a current-steering DAC can be seen as an array of fixed current sources whose output current is steered between two complementary outputs proportionally to the value of the digital input data. The output signal thus generated is the analog representation of the digital input data.
Nyquist theory tells us that a DAC (or ADC) can accurately convert a signal whose bandwidth is lower than half the sampling rate. However, in real life, the dynamic characteristics of the DAC can limit the effective signal bandwidth to much lower frequencies.
The dynamic performance of the DAC is, in turn, bounded by effects such as matching characteristics of the current sources, device electrical noise, output impedance roll-off, unbalanced charge injection during switching and other timing mismatches. These limitations have not been economically possible to address in high-speed integrated DACs and therefore DACs were only suitable for baseband signal processing.
To work within the architectural constraints of the analog blocks (including the integrated DAC), the communication channel for most baseband signal processing protocols lies in a relatively narrow bandwidth (e.g., 20 MHz for LTE; 40 MHz for WiFi 802.11n, 10 MHz for CDMA, etc). These bandwidths are suitable for traditional DAC transmit path architectures performing direct modulation of the relatively narrow baseband signal directly to RF, as illustrated in Figure 2. In these architectures, channel selection is performed in the analog domain by selecting the RF channel frequency (fc) through programming the local oscillator, typically implemented with a programmable phase locked loop (PLL).
Figure 2: Block diagram of a transmit system employing traditional direct modulation architecture
High-speed transmit DAC implementations
The recent introduction of new DAC design techniques allows current-steering DACs to process broader band signals. These techniques include:
These other design techniques improve the dynamic performance of the DAC even for very high-frequency signals. Other techniques, such as using return to zero output, can extend the use of the DAC for signals in higher Nyquist bands (in under-sampling mode).
Advanced high-speed transmit DACs support broader band signal transmission for new communication protocols such as LTE-advanced or WiFi 802.11ac (requiring up to 100 MHz and up to 160 MHz aggregated channel bandwidth, respectively), or wireline communications such as G.hn, MoCA 2.0 or Home Plug AV2 (requiring channel bandwidth up to over 100 MHz).
In addition to supporting broader signal bandwidth, high-speed transmit DACs also enable the implementation of the modern transmit path architectures described above.
Figure 3 depicts an example transmit path that incorporates architectural changes that are becoming more common in transmitter implementations. In this transmit path, a broadband channel (or several neighboring channels) is transmitted. Channel selection within the RF band is performed on the digital domain. This simplifies the function of the analog mixer to just mixing the fixed RF band selection.
This implementation makes use of a high-speed transmit DAC's most relevant characteristics:
Figure 3: Block diagram of a transmit system employing a modern architecture using a high-speed transmit DAC
High sampling rate
The analog filtering that occurs after the DAC in Figure 3 performs two types of signal filtering:
Analog anti-aliasing filtering can be significantly simplified by oversampling the signal, due to the wider separation between the sampling images from the intended signal. When oversampling is used in a DAC, an additional digital interpolation filter is used to up-sample the digital signal to the correct oversampling rate.
In the absence of a steep analog filter, the DAC out-of-band output noise density and other inter-modulation distortion tones may not be adequately attenuated. To guarantee compliance with regulatory transmit masks, a high dynamic performance DAC, with a lower output noise floor and higher linearity may be mandatory.
Broadband signal processing
Using higher-speed DACs also allow designers to simplify analog RF mixing in systems where data is transmitted in several adjacent channels. In these cases, channel selection is made on the digital domain, by means of a digital mixer (Figure 3). The output of this mixer is an IF signal centered on the center frequency of the selected channel. The IF signal is converted to the analog domain and then modulated up to the frequency band of interest by a mixer whose frequency selection range can be coarse (center of each band) since it does not have to select each channel within the band independently.
To support simplified transmit architectures for broadband communications, DACs must offer the following characteristics:
Modern DAC implementations rely on multiple techniques to improve performance at high sampling rates. Dithering, careful phase alignment, and other techniques all contribute to improve the dynamic DAC performance even for very high-frequency signals. Using these techniques, Synopsys has demonstrated a 14-bit DAC at sampling rates beyond 500 MSPS which achieved a third order intermodulation distortion (IMD3) better than -75 dBc for signals higher than 200 MHz in a standard CMOS 65-nm technology. Such performance makes it ideal for use in modern transmit architectures such as the one described above, as well as for the most recent broadband wireless and wireline protocols that can define channel bandwidth up to 100 MHz.
For more information on Synopsys DesignWare® Data Converter IP solutions, please visit: http://www.synopsys.com/dataconverter
Synopsys delivers semiconductor design software, intellectual property (IP), design for manufacturing (DFM) solutions and professional services that companies use to design systems-on-chips (SoCs) and electronic systems. The company's products enable semiconductor, computer, communications, consumer electronics and other companies that develop electronic products to improve performance, increase productivity and achieve predictable success from systems to silicon
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