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Smashing Through the Mobile Device Memory Bottleneck
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Kevin K. Yee — Cadence

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The mobile revolution has been the driving force in consumer electronics since the debut of the Apple® iPhone®, but it is now transforming business IT as well. A recent forecast by Gartner predicts that two-thirds of all mobile workers will utilize a smartphone by 2016 and that business expenditures for tablets will triple by then to $52M. This will shift market demand from content consumption to content creation on "superphones" and tablets, and it will require greater processing performance from these devices. At the same time, relentless demand for longer battery life makes delivering that performance harder to achieve.

ARM is addressing CPU performance and power with its big.LITTLE processing approach, but the memory subsystem remains a critical bottleneck to achieving system performance and power targets. In fact, the move to multicore processors and accelerators makes the memory bottleneck effect even more pronounced since greater demands are placed on the memory subsystem. To address this problem, Cadence is extending its leadership in the double data rate (DDR) IP space by delivering a new and complete end-to-end DDR solution optimized for mobile SoCs.

Smartphone. Consider a typical smartphone consisting of a digital baseband domain, a modem, and an application processor (Fig. 1).

Fig. 1: Example Mobile Phone Diagram with Memory Subsystem

The modem handles the DSP voice and data processing for the desired standards that need to be supported-GSM, CDMA, 3G, 4G, or LTE. The application processor handles various functions for video, image, and data processing. Newer mobile devices may have a general purpose CPU as well as a dedicated media processor for video encode/decode or 3D rendering for games. All of these processors have one significant bottleneck-the memory subsystem. At the same time, the memory access can become a considerable drain on the power budget.

Memory Subsystem. The memory subsystem is one of the key components of any system and, in many cases, has the largest impact on system performance in most SoCs. As shown in Fig. 1, the memory subsystem includes an SoC fabric interface with arbitrator, command sequencer, SDRAM controller, and physical layer (PHY). Ironically, it can present itself as one of the greatest opportunities to conserve power in the system if designed correctly. Any solution considered needs to be up to the challenges presented by the mobile market-power, performance, cost, and size.

As a result, today's memory subsystem needs to be quite elegant. It must implement a fully pipelined architecture with flow control for commands and data, and support command reordering with built-in sequencing engines to optimize transaction cycles for bandwidth and latency. At the same time, it must maintain relative priority and memory coherency and implement multi-port arbitration functionality to efficiently provide data from memory to the various on-chip functional blocks. A successful solution will also need to support the latest memory devices as well as legacy devices to provide tradeoffs in availability and cost.

In addressing the memory subsystem, the DDR SDRAM interface will have a fundamental impact on the power and performance of the system. A multi-disciplined, system-level approach is required.

Cadence Solution. The Cadence mobile DDR solution (Fig. 2) includes a controller supporting LPDDR3/LPDDR2 and a PHY supporting speeds up to DDR-1600. The solution is delivered in the traditional combination of soft controller and hard PHY as well as a highly optimized hardened controller/PHY implementation.

Fig. 2: Cadence Mobile DDR IP Solution

LPDDR Controller Value. The Cadence LPDDR controller (Fig. 2) is designed to support the most popular low-power DDR SDRAM standards for mobile devices, LPDDR2 and LPDDR3. To keep memory in the lowest power state possible and extend battery life, the controller includes automated support for power-down, self-refresh, clock gating, and deep power-down. An advanced low-power module can reduce active power by up to 50% and standby power by up to 10x. To obtain maximum performance, the controller contains a priority arbitration engine and a reordering queue designed to maximize bandwidth while still offering low latency for critical commands. Other key features include quality of service (QoS), flexible paging policy, auto-precharge per command, priority per command, and coherent bufferable write completion. The controller also includes a security module used in the latest smartphone and tablet chipsets.

DDR Mobile PHY Value. The Cadence DDR mobile PHY (Fig. 3) is a fully hardened macro. It comes with attached I/O pads and is available in TSMC's 28nm High-Performance Mobile (HPM) process. It supports both LPDDR2 and LPDDR3 standards at transfer speeds up to 3.2GHz (DDR-1600).

The Cadence DDR mobile PHY is an all-digital solution connecting the DDR I/O pads to the DDR PHY interface (DFI) of the memory controller, including alignment of write data, read data capture, and DQS gating. Using a DLL-based design keeps both power and area to a minimum. As an integrated off-the-shelf solution, the PHY can simply act as a pass-through block for data. This is the beauty of the integrated offering-the designer can view the PHY as a pass-through and not be concerned with the typical challenges associated with integrating a separate PHY with the controller.

Fig. 3: Cadence Top-Level Mobile DDR PHY IP

Integrated Mobile DDR IP Value. The integrated IP solution offered by Cadence is a complete and single IP source for mobile DDR subsystems that combines an LPDDR controller and PHY. It is a fully integrated and hardened off the shelf solution. Because the controller and PHY require different engineering skills, tools, and methodologies-and, in most cases, are handled by different engineering groups-an integrated off-the-shelf solution eliminates the difficult challenges of engineering resources, time constraints, and design and verification bottlenecks.

The fully integrated solution eliminates the most difficult integration challenges. Designers will not need to iterate through synthesis, layout, clock tree synthesis, and other steps for the controller and PHY, saving considerable time, resources, and effort. The Cadence solution provides the complete netlist and GDSII data. It is optimized as a compact solution providing a minimal footprint.

Summary. Designers would love to be given everything they need, gift wrapped and ready to go. The Cadence mobile DDR IP solution is that gift if you are developing a mobile SoC. With an integrated LPDDR controller and PHY, it addresses the critical bottleneck in today's mobile systems. By utilizing the Cadence mobile DDR solution, you can get a single IP that addresses the needs of your memory subsystem for your SoC and ensures that you will achieve the highest performance, the lowest power consumption, and the fastest time to market.

Learning More:

Cadence has a complete portfolio of DDR controllers and PHY IP for your specific memory needs. To learn more about Cadence IP, please visit our website or contact us.

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About the Author

Kevin K. Yee

Kevin Yee is a member of the Product Marketing team for Design IP at Cadence Design Systems and is driving worldwide IP enablement. Kevin is an expert in IP, VIP, semiconductors, and FPGAs. Kevin has worked with world leading mobile customers for low power applications at the IP, chip and system levels and has been involved with MIPI, PCI-SIG, USB I/F, and various standards organizations. Kevin holds a BSEE from University of California, Davis.