The cellular phone has revolutionized the way of life for people around the world, with more than 50% of the world’s population using cellular phones (1). The way we communicate has been forever changed. We can exchange information, take pictures, navigate, consume content, purchase items and manage business in the palm of our hand.
While the features and applications that reside on cellphones and smartphones differ greatly, the display and camera remain the most common user interfaces. The multi-megapixel image sensor embedded in almost all of today’s cellular phones allows taking pictures and video streams for fun, family and business applications. The display in smartphones is used in multiple ways. First, it is used as a display to watch videos, read content and conduct video conferencing calls. Secondly, it is used as the input to the operating system, via a touch screen interface.
Display and Camera Interfaces
Traditional camera and display interfaces utilize a parallel, high pin count link and, in some cases, low-voltage differential signaling (LVDS) to minimize pin count. These interfaces do not scale very well, have limited performance and are complex with regard to the number of pins utilized. They also can have reliability issues with many wires connected through the cellular phone hinges. In addition, the power and performance specifications of traditional parallel buses have made it difficult to achieve long battery life while keeping the cost to a minimum.
Designers are transitioning from a parallel interface to a serial interface to help achieve lower power consumption and higher throughput. A serial interface design is complex, but enables high performance, architecture scalability while successfully meeting design targets and reduced electromagnetic interference (EMI). Display and camera modules are typically interfaced from the application processor, which manages the receiving and transmitting of images, movies and other content as shown in Figure 1.
Figure 1. Display and Camera interfaces in mobile electronics
Motivation for Standard Interface
To address broad market requirements, mobile electronics OEMs will typically use hardware components from multiple vendors which all need to seamlessly integrate together. One way to achieve the seamless integration is by standardizing the chip-to-chip interfaces for all inter-function connectivity in the mobile electronics environment, enabling the following:
easily upgradable features
reduced pin count
increased system reliability
ease of test and debug
lower electromagnetic interference (EMI).
For example, major handset OEMs will use SoCs from different semiconductor companies to meet different radio standard requirements. Since these SoCs come from different vendors, they vary in feature sets, performance and interfaces to peripherals such as displays and cameras. Therefore, OEMs need to find display and camera modules that match the interface and capabilities of the SoC chosen for each platform.
The benefit of standard interfaces is clear from the design, technical, manufacturability and, especially, cost perspective, as it is expected that ICs using standards-based interfaces will ship in higher volume because they allow for a cost reduction of the entire system over time. The most notable chip-to-chip serial interfaces in the mobile industry are the ones defined by the MIPI Alliance. Interfaces designed to the specifications defined by the MIPI Alliance are used to replace proprietary interfaces and address reliability concerns of cellular phone designs as well as employ serial interfaces for low power and high throughput. The interfaces based on the specifications from the MIPI Alliance are experiencing significant market traction as major players in the mobile electronics industry are supporting and driving adoption throughout the entire value chain. This creates a comprehensive ecosystem of MIPI-based solutions in all levels of design, test, IP, verification, etc.
Mobile Industry Specifications
The MIPI Alliance (www.mipi.org) is comprised of companies that are working together to define and promote a family of specifications that have been developed for the mobile device market. Today, the adoption of the specifications from the MIPI Alliance is clear for mainstream interfaces such as display, camera and baseband radio interfaces. MIPI-based interfaces have become the de-facto standards for the camera and display interfaces in mobile electronics, which require the SerDes D-PHY physical layer as well as the camera serial interface (CSI-2) protocol layer and the display serial interface (DSI) protocol layer. Providing proven intellectual property (IP) that covers the MIPI D-PHY and CSI-2 and DSI controller interfaces on common processes allows for easy, rapid and low-risk implementation. Thus, semiconductor companies can quickly adopt the interfaces based on the MIPI Alliance specifications and capture market share easily and effectively.
MIPI D-PHY, DSI and CSI-2
The MIPI D-PHY is a physical layer implementation that provides a source-synchronous, point-to-point connection between master and slave (or host and device) configurations for MIPI protocols such as CSI-2 and DSI.
The D-PHY specifies the characteristics of the transmission medium, electrical parameters for signaling and the timing relationship between clock and data signals. The DSI and CSI-2 interfaces define the protocol layer that connects to the D-PHY physical layer to enable transmit and receive of multiple data streams by tagging and interleaving so each data stream can be properly reconstructed.
A typical D-PHY configuration consists of a clock lane and 1 to 4 data lanes. The master is primarily the source of data, and the slave is the sink of data. D-PHY lanes can be configured for unidirectional and bidirectional lane operation, originating at the master and terminating at the slave. The D-PHY link supports a high-speed (HS) mode for fast data traffic and a low-power (LP) mode mainly for control and command transactions. In HS mode, the low-swing differential signal is able to support data transfers from 80 Mbps to 1 Gbps. In LP mode, all wires operate as a single-ended line capable of supporting 10 Mbps asynchronous data communications. The D-PHY core can implement the PHY protocol interface (PPI) to easily interface to the required protocols (e.g., DSI and CSI-2 controllers). The Display Serial interface (DSI) system diagram is shown in Figure 2.
Figure 2. Display Serial Interface (DSI) System Diagram
Display Serial Interface (DSI) is a high-speed, high-resolution serial interconnect bus offering connectivity to display devices. DSI uses MIPI standard D-PHY for physical layer high-speed differential interfaces with up to four data lanes and a common differential clock lane. Pixel data and commands are serialized into a single physical stream, and status can be read back from the display. The protocol supports host and device technologies needed in the application processor, display panel and bridging applications. It also supports display devices operating in video mode and command mode. Video mode and command mode display devices are found in mobile electronics, as the need in more complex and lower power implementation is dependent on the system implementation and application.
Figure 3. Camera Serial Interface (CSI-2) System Diagram
The Camera Serial Interface (CSI-2), seen in Figure 3, is a high-performance serial interconnect bus for mobile applications connecting camera sensors to digital imaging modules, such as a host processor or image processor. CSI-2 uses MIPI D-PHY for physical layer and HS differential interfaces with up to four data lanes and a common differential clock lane. A separate I2C-based Camera Control Interface (CCI) is used for interfacing and controlling signals between the host and camera. It supports host and device technologies needed in the application processor, camera sensor and bridging applications.
All these off-the-shelf standard interfaces enable low power, low pin count and low EMI-scalable interfaces with high-bandwidth capability.
IP Vendors Help Drive Adoption of MIPI Protocols
A proven solution from single-vendor lowers the risk and cost of integrating MIPI interfaces into host processors and SoCs. Having silicon-proven and fully characterized PHYs available for a broad range of foundries and process technologies enable rapid SoC platform design. This helps designers to speed the time-to-market of advanced multimedia SoCs targeting cellular phone, smartphone, tablets and other mobile electronics. Figure 4 shows a typical mobile device system diagram highlighting the MIPI IP components implemented on host SoCs and device ICs.
Figure 4. Typical MIPI solutions in mobile device
Meeting the Needs of Mobile Semiconductors
Balancing requirements for faster, lower power and lower cost devices is part of the formula to achieving success. Managing systems and resource allocation based on tasks that provide differentiation, versus standard tasks that can be outsourced or acquired, is another part. Partnering with a trusted IP provider enables rapid market penetration and helps ensure the first silicon works to specifications.
Mobile electronics market growth will be fueled by the wide adoption of MIPI Alliance specifications, which will eliminate incompatibilities and fragmentation in interfaces, increase system reliability and quality, improve productivity by focusing energy on value-added differentiation and facilitate innovation. This is also evident by a recent report by iSuppli that projects the continued and rapid adoption of the MIPI DSI interface, expecting it to reach over 63% penetration by 2013 (2).
Improving the ability of electronics manufacturers to respond to end-user needs effectively and rapidly will meet user satisfaction; enhance the user experience, thus increasing the usage of mobile electronics.
Hezi Saar serves as a product marketing manager at Synopsys and is responsible for its DesignWare® MIPI controller and PHY IP product line. He brings more than 15 years of experience in the semiconductor and electronics industries in embedded systems. Prior to joining Synopsys, from 2004 to 2009, Hezi served as senior product marketing manager leading Actel’s Flash field-programmable gate array (FPGA) product lines. Prior to that, Hezi served as a product marketing manager at ISD/Winbond and as a senior design engineer at RAD Data Communications. Hezi holds a Bachelor of Science from Tel Aviv University in computer science and economics and an MBA from Columbia Southern University.