The microelectronics industry
is noteworthy for its innovations in both technology and design methodology.
So why are so many chip manufacturers still using masked ROM for storing
IDs, algorithmic coefficients, code and other important information
instead of the more flexible, secure and field-programmable, antifuse-based
OTP (one-time programmable) memory?
Masked ROM represents a very
cost-effective way of permanently storing inviolate code or arithmetic
operation coefficients that never change. The ROM cell is implemented
within a standard CMOS logic process and, thus, does not add any additional
wafer processing cost. However, if the contents of a ROM need
to be changed, such as for updating stored code for a processor, the
chip with the embedded ROM needs to be modified to reflect the new ROM
programming and run through the process again. This significantly
increases the cost of the product with the ROM and adds several weeks
or months before the product reaches the market.
ROM cells are small and, once
programmed, are irreversible and hence reliable. However, they
have two major shortcomings: low security and lack of field programmability.
Because a masked ROM is hardwired
during chip fabrication, it is relatively easy to reverse engineer to
see the programming of a ROM block. By peeling away the top layers
of the chip, the states of the individual bit cells, and hence the ROM's
program, can be read directly with an optical microscope or by using
SEM or FESEM (Field Emission Scanning Electron Microscope) equipment.
Since the ROM's program may represent very valuable intellectual property
- either directly as processor code or indirectly as encryption key
protection of valuable data - the lack of high security is a critical
deficiency for many applications.
The other major problem with
ROM is that it is programmed during wafer processing and cannot be modified
afterwards. If used for code storage, this means that code must
be frozen when silicon is ready, which eliminates the possibility of
modifying this code during or after silicon verification in the target
system. This also eliminates ROM as a viable choice for storing
parameters or encryption keys that may require updates during the life
of the end product, unless the product manufacturer is willing to incur
the additional expense of redoing the chip with updated information
reconfigured into a new ROM.
Replacing embedded ROM with
antifuse-based OTP memory IP eliminates the security and field-programmable
problems associated with masked ROM. While there are different
variations of antifuse-based OTP memory available, the following discussion
will show that one type - a split-channel cell based on oxide breakdown
to program a bit - is the smallest and most reliable version of this
type of memory IP.
One type of antifuse OTP is
based on two transistors with different oxide thicknesses, one thick
(the access transistor) and one thin (the storage transistor).
The two gates are tied together (the Word Line) while the drain of the
thick oxide transistor is used as the Bit Line. To program a bit
as a "1" you apply a voltage to the tied gates high enough (6-8
volts).to break down the thin oxide transistor but not the thick oxide
device. You can program the OTP memory after chip processing,
either during test or in the field. Field programmability of antifuse
OTP memory is a big advantage over ROM, since it extends the development
time of system software and supports in situ operations such as sensor
conditioning calibration and late programming of chip IDs and encryption
The 1.5T cell does have advantages
over a ROM cell, but it is not the optimum way to implement an antifuse
OTP memory cell. Besides being significantly larger than a high-density
masked ROM cell, the cell's programming is multimodal because the
thin oxide transistor can break down in one of three distinct regions
channel (what is desired)
To a Halo implant
(used for leakage control)
Figure 1. Since the 1.5T
antifuse OTP cell can have its oxide break
down in three separate regions during programming, you get a multi-modal
distribution of programmed cell current, compromising cell programmability
Oxide breakdown to the LDD
region (3) forms a resistive link between the n+ polysilicon
and the n+ diffusion, resulting in a high current tail.
Breakdown to the channel region (1), which is the dominant (and desirable)
programming mechanism, forms a diode-connected NMOS transistor characterized
by a specific threshold voltage and resistance. Breakdown in the
pocket or Halo region (2), with its higher p+ concentration,
results in higher resistance or higher Vt than in the channel
region, leading to a low current tail.
With a 1.5T device you have a tri-modal distribution of the programmed
cell current that can result in large and unpredictable tails in the
current distribution of programming cell current.
Split Channel 1T-Fuse™
A better structure for an antifuse
OTP cell is one that uses a single transistor with both thick and thin
oxide over the channel. This device is represented by the 1T-Fuse™
cell developed by Sidense (Figure 2).
2. The 1T-Fuse OTP cell uses a single, variable gate
oxide thickness transistor for improved cell reliability and yield
along with reduced size.
Replacing the two separate
transistors with a single split-channel transistor above a single
gate region offers several reliability, process portability and cost
advantages over a 1.5T OTP bit cell with its separate thick and thin
By eliminating the diffusion
between separate thick and thin oxide transistors, the 1T-OTP cell programs
only in one region - over the thin transistor's channel. This
results in well-controlled, uni-modal programming with no tails in the
programming current distribution, resulting in higher yield and reliability
than what you can get with a 1.5T bit cell. A further advantage
is better portability between silicon foundries.
Foundries use the Halo implant
to help control device leakage at the edge of the gate region, and each
foundry has its own version of this manufacturing equipment-specific
implant. With a 1.5T bit cell, you have to repeat qualification
not only for every process node at a foundry, but for every foundry
with the same process node. By eliminating the Halo implant in
the 1T-OTP device, you can more easily move between silicon foundries
at a given process node.
Another advantage of the 1T-OTP
bit cell is a significant size reduction over the 1.5T OTP bit cell
(Figure 3). A single transistor 1T cell takes less area and is
very close to the size of a masked ROM cell. This gives the 1T cell
two additional advantages over the 1.5T cell. Chip cost is lower,
particularly for chips that use high-density OTP blocks, such as for
code storage, since the added area for the OTP memory block is smaller.
Cost reduction of 1T-OTP over 1.5T OTP memory also manifests itself
in higher yield, since the smaller the block the less likely it is to
contain a random defect introduced by the manufacturing process.
3. A 1T-OTP cell is about the same size as a high-density masked ROM
cell and significantly smaller than a 1.5T OTP cell, resulting in higher
yield and lower cost.
is a huge advantage of antifuse OTP memory over ROM, there are certain
applications in which users need to have multi-time or few-time programmability.
Examples include software updates for processors and encryption key
changes for Digital Rights Management (DRM) protocols, such as HDCP.
Because of its small bit size, this can be done on a system level with
1T-OTP memory. The trick is to include some un-programmed sections
of the OTP block. When you need to update some of the memory core's
contents, load the new information into a previously un-programmed section
and update your system software to point to the updated section in place
of the previously used section. By estimating the number of times
you will need to do updates over the lifetime of a product, you can
design in the right amount of OTP memory for your particular application.
Jim Lipman recently joined
Sidense as Director of Marketing. Prior to Sidense, Jim worked
at Cain Communications as Vice President of Client Services, TechOnLine
as Content Director, and at EDN Magazine as ASIC and EDA Editor.
He also was employed by VLSI Technology, where he held various training,
marketing and public relations positions, and has done chip designs
at both Hewlett-Packard and Texas Instruments.
Jim received his BSEE and MSEE
degrees from Carnegie-Mellon University in Pittsburgh and his Doctorate
in Electrical Engineering from Southern Methodist University in Dallas.
He also has a Masters of Business Administration from Golden Gate University
in San Francisco. Jim is a senior member of the IEEE.