By Marc Greenberg, Director, Technical Marketing Denali Software, Inc.
Introduction
There are two types of DRAM chips commonly used in embedded systems. PC DRAM chips are the DDR1, DDR2 or DDR3 parts that are used in almost all PCs and servers. Low-Power DRAM chips are the LPDDR1 and LPDDR2 parts used most often in cell phones and portable applications.
PC DRAM often is the lowest cost DRAM memory and often finds its way into consumer products, even though in many cases it's not technically ideal for that purpose.
Low-Power DRAM is often a better technical fit for embedded-type applications and a requirement for low-power applications, however, Low-Power DRAM often comes at a higher cost than PC DRAM. Although LPDDR2 has recently been introduced into the marketplace, the mainstream Low-Power DRAM today is LPDDR1 and it has been 6 years since its introduction.
The standard voltage of DDR3 and new low-voltage variants of PC DRAM even offer lower voltage operation than LPDDR1. One of the questions often asked is, could you be better off with PC DRAM for low-power embedded applications?
First Principles
In this article, let's look at the supply voltage of the different memory types. . Reducing supply voltage is one of the surest ways of reducing power consumption, as Power (P) is the product of Current (I) and Voltage (V), (P=I*V). In fact if we take the gross assumption that the losses in a memory can be modeled as resistive (R) losses, and since I=V/R, then Power is proportional to V2/R.
Table 1 (see below) shows supply voltage and V2 relative to LPDDR1 for the various memory types. At a first glance, it seems that DDR3 or the low-voltage variant of DDR2 PCDRAM ("LV-DDR2" or "DDR2L") would result in about a 30% power saving over LPDDR1. But is it really telling us the whole story?
Table 1: Supply voltage for various memory types, and V2 relative to LPDDR1
Looking at the Memory Under Different Operating Modes
Looking beyond the supply voltage, we must also consider how the memory uses power in different operating modes. Memory datasheets include specifications for the current consumption (Idd) while the memory is performing different tasks. In this article, consider the following use cases:
The system is reading continuously from memory without activating or pre-charging new banks ("Idd4R").
There is one bank active in the memory and there is no activity on the memory bus ("Idd0"). This happens, for example, when there are no commands to process but the memory has not been put into a low-power mode.
All banks in the memory are pre-charged and CKE is low (Pre-charge powerdown) ("Idd2P"). This is a low-power mode that is quick to enter into and to exit from, particularly for LPDDR memories.
Self-Refresh mode, full array, 45 degC ("Idd6"). This mode is typically used for long-term idle periods (for example, when the device is in standby mode) and has a short exit time for LPDDR memories and a long exit time for DDR2/DDR3 memories.
This article explores five different memory configurations, each capable of providing 10.6Gbit/sec of peak bandwidth:
A 32-bit wide 1Gbit 1.8v LPDDR1 part running at 166MHz(DDR-333)
A 16-bit wide 1Gbit 1.8v DDR2 part running at 333MHz (DDR2-667)
A 16-bit wide 1Gbit 1.5v DDR2L part running at 333MHz (DDR2-667)
A 16-bit wide 1Gbit 1.5v DDR3 part running at 400MHz (DDR3-800)
A 16-bit wide 1Gbit 1.5v DDR3 part running at 333MHz (DDR3-667)
Idd values are not typically published for DDR3-667 so the Idd current values used are extrapolated to DDR3-667 from the higher speed grades.
When doing this kind of comparison, it is sometimes difficult to be comparing the exact same operating conditions across memory families, since sometimes the different Idd use cases are different (notably, Idd0 and Idd4R are calculated differently for DDR3 than for other memories). The comparison uses values from openly available memory datasheets for production parts from the same manufacturer.
Table 2 (see below) shows the results of these comparisons. As expected, the PC DRAM DDR2 part uses the most power in most cases, being a 1.8v part that is not optimized for low power. However, it can be seen that the LPDDR1 part is the lowest power device in 3 of the 4 categories, and in the Powerdown and self-refresh modes, LPDDR1 uses about 8X less power than the PC DRAM memories.
Table 2: Comparisons of operating current and power consumption for a range of memory system configurations and operations. Green indicates the lowest power or current for a particular column; red indicates the highest power or current for a particular column.
Considering Different Use Models
The next thing to consider is how your system will use the memory. If you look at table 2, when the system is fully active with reads or alternating between the read(Idd4R) and idle (Idd0) states, the power consumption of LPDDR1 and low-voltage DDR2L are similar, so you might conclude they are equivalent parts.
One thing to contemplate is that a memory controller with intelligent power management - such as Denali's DatabahnTM - can identify periods of time where the memory is not being used (Idd0) and move the memory into a low power state such as Powerdown (Idd2P) or Self-Refresh (Idd6). When that occurs, the LPDDR1 is again using significantly less power than the LPDDR2 part.
To obtain a full picture of power consumption in a system, it's necessary to consider how much time the controller will spend in each different power situation. There are more operating modes than what have been shown above, but a simple example is shown in Table 3, where we'll consider 4 different use models of the memory and provide an average power for each use model:
Table 3 (see below) shows us that for all the mixed use models considered that LPDDR1 provides the lowest power consumption.
Table 3: Power consumption for different use cases.
Automating Memory Access for Even Less Power
Denali's Databahn memory controllers for DDR1, DDR2(L), DDR3(L), LPDDR1 and LPDDR2 help to control power usage with intelligent memory traffic management. With capabilities such as automatic power mode selection, grouping and splitting of accesses, and selectable open or closed page modes, Databahn can provide bandwidth improvement, low latency and power reduction even with non-optimal memory traffic from the system.
Future Memories
Several manufacturers have announced Low-Voltage DDR3 parts (DDR3L, 1.35v) as well as LPDDR2 parts (1.2v), although there are no publicly available datasheets for these parts at the time of writing, the datasheets do exist and can be requested from memory manufacturers directly. Denali's database for our Memory Modeler Advanced Verification (MMAV) software contains models for 23 different LPDDR2 memories from 6 different manufacturers.
We expect DDR3L to compare favorably with all the memories above, except for LPDDR1 in the standby case, and expect LPDDR2 to have the lowest power usage in all use cases.
Other Considerations
Each memory class is slightly different and may have use limitations or extra features that can reduce power further. For example, DDR2 and DDR3 parts have on-chip DLLs that need to be disabled for operation below 125MHz and 303MHz respectively. Those same on-chip DLLs on DDR2/DDR3 need to settle for several hundred clock cycles when exiting self-refresh, whereas LPDDR1 and LPDDR2 can exit from self-refresh more quickly. LPDDR families typically allow for Partial Array Self-Refresh (PASR) that can provide a significant power saving in Self-Refresh mode. A good understanding of memory protocol is required to get an accurate estimate of the power usage of each memory.
Also, not considered in this article, is the power consumption of things that exist on the SoC or ASIC; the memory controller, physical interface (PHY), and I/O pads all consume power and have not been considered here.
Summary
This article has aimed to provide insight on the relative power consumption of different memory classes, and show a method to create use cases when analyzing how DDR SDRAM will consume power in their system.
Marc Greenberg is the director of Technical Marketing for the IP products group at Denali Software, Inc. A Masters graduate from the University of Edinburgh in Scotland, Marc's career includes 5 years at Denali and 10 years at Motorola in IP creation, IP management and SoC Methodology roles in Europe and the USA. Marc represents Denali at JEDEC and has been working with Denali's Databahn memory controller since joining Denali in 2003.
