The time for Silicon-on-Insulator (SOI) technology has finally arrived. As process technology shrinks, the power density of chips is climbing. Alternate technology approaches are going to be needed to address this challenge. Mike Muller, , ARM CTO, at the March 25 EE Times "Designing with ARM" virtual conference postulated: given the same power budget used for the 45 nm design today, if an 11 nm design has 16X the transistors running at 0.6X the power, "I can actually use only 10 percent of them in my new design," Muller said. "The rest is dark silicon. We need to find ways of lighting that silicon up."
Fortunately, as Muller postulated, SOI technology is an obvious contender to meet the power density test. For seven process generations, SOI has been quietly serving high-performance applications such as enterprise servers, networking and storage systems, and game consoles delivering on challenging speed requirements consuming up to 40% less power than bulk silicon technology. With scores of SOI based products deployed in the marketplace, SOI is a time-tested technology with proven custom and digital design flows. In addition, a growing base of IP is becoming available for a new set of consumer product applications such as digital TV, high-performance mobile internet devices, printers, and ultralow-power applications such as wristwatches and automotive applications. In addition, SOI’s favorable radiation-tolerant characteristics have been recognized by companies such as Boeing for extraterrestrial semiconductor applications.
So, what makes SOI process deliver this superior performance/power profile? Bulk technologies start with a single-crystal silicon substrate, the SOI starting material has an embedded oxide layer just below the silicon surface. The significance is a reduction in leakage current and power/performance advantages over devices designed and built in bulk wafers.
Internal studies at IBM have compared 45 nm SOI-based circuits to the same circuits in 45 nm bulk silicon showing yield 30% performance benefit using transistors of comparable leakage. For designs not requiring higher performance, the SOI advantage can be turned into a lower-power design point. Additional IBM studies indicate lower soft error rates are intrinsic to SOI technology, with a 5–7× improvement over bulk. Furthermore, SOI-based devices generally have better temperature sensitivity so that they can be operated at high temperatures and latch up does not exist because device isolation prevents parasitic bipolar device formation between FETs.
Last week the SOI Industry Consortium announced the launch of its "Ready for SOI Technology" program, a global initiative to broaden access to energy-efficient silicon-on-insulator (SOI) technology for the electronics industry. Recognizing that SOI technology has not reached its full potential in the marketplace, a core group of SOI Industry Consortium (SOIC) members: ARM, Cadence and IBM came together to address some of the perceived obstacles to wider adoption of SOI process technology. In 2008, GSA and SOIC conducted a survey identifying EDA tools, IP and education as barriers to adoption of this promising technology. Today, these issues are being addressed via the SOIC’s aggressive program aimed building a broad and complete ecosystem for SOI design. At launch of the program, ChipEstimate.com fielded a web portal dedicated exclusively to SOI IP and boasting more than fifty IP elements from IBM, ARM, Cadence, Boeing and Synopsys. The rich set of IP available from IBM, has been silicon proven within its ASIC technology offering and is now available to foundry customers as well. In addition, designers can take advantage of IBM’s SOI foundry offering with embedded DRAM. IBM’s SOI technology with eDRAM is a key enabler for multi-core processors and other integrated circuits and can result in improved systems performance and energy savings for a range of applications including networking, printer, storage, consumer and mobile products. Today the ChipEstimate.com/soi portal can enable designers to evaluate SOI process technology against other technologies for their next design.
To address industry education, the SOI Consortium is mounting a program to bring SOI design knowledge to designers. On April 28th on the Cadence Design Systems campus, a Ready for SOI Jump Start Training will be held. The half-day training program will also be webcast live for those outside Silicon Valley and archived for viewing later. Experts from IBM, ARM, Cadence, IBM and SOI Consortium will be on hand to deliver an insightful overview of current SOI knowledge. Included in the program will be:
overview of the current successful applications of SOI technology
specific details on the technology from experts at IBM
how to gain access to available design enablement including PDKs, libraries, and memory compilers to get you off the ground
particulars on design flows, design considerations and available design tools available
for IP suppliers, resources available for porting your IP to SOI and listing it on the ChipEstimate.com SOI portal
To attend The Ready for SOI Jump Start Training in person or on-line Register here>>>
Susan Runowicz-Smith joined Cadence in 2002, as Marketing Group Director, where she has been instrumental in driving industry-level initiatives including The Ready for SOI Program, the Power Forward Initiative and Silicon Design Chain. During her 20+ years in the EDA industry, she has broad experience in business development, product marketing and EDA tool development at Simplex Solutions, Synopsys, LSI Logic, Zycad, Schlumberger and DEC. She received her B.S. in Applied Mathematics from the University of Massachusetts at Lowell.
The time for Silicon-on-Insulator (SOI) technology has finally arrived. As process technology shrinks, the power density of chips is climbing. Alternate technology approaches are going to be needed to address this challenge. Mike Muller, , 
So, what makes SOI process deliver this superior performance/power profile? Bulk technologies start with a single-crystal silicon substrate, the SOI starting material has an embedded oxide layer just below the silicon surface. The significance is a reduction in leakage current and power/performance advantages over devices designed and built in bulk wafers.