Kate Kelley — Xilinx
Xilinx® FPGAs offer up to 2 million logic cells in capacity—and they continue to grow. Designs of this complexity usually require a team of developers, and often, a team leader, who is responsible for the synthesis and implementation of the entire design. To make matters more challenging, the developers can be located internationally, with different portions of the design developed in different locations, and even by different companies. The Xilinx Team Design flow introduced in ISE® Design Suite 13.1 focuses on solving these challenges.
The Team Design flow has three major steps: the initial design setup, team member implementation, and assembly of all the team member modules into a final design. The initial design setup provides the framework for each team member to implement their portion of the design independently of other team members—but in context with the top-level design. At intervals during the design cycle, the entire design can be assembled by using the implementation results of each team member. See Figure 1.
Figure 1: Team Design Flow
The most important step of the flow is the initial planning stage. This step includes HDL design rules, design partitioning, synthesis setup, floorplanning, high-level timing requirements, directory structure for the team, initial implementation, and finally, the projects or work space required for each team member. The initial setup is typically done in the PlanAheadTM software. If desired, the project can be moved to a script-based flow.
For the best quality of results (QoR) and utilization, certain design rules must be followed. The goal of these rules is to keep all the critical timing paths internal to each team member module for easier assembly. These rules are especially important if there are high QoR requirements between the modules:
Not only is it critical to follow good design guidelines, but it is also important to determine the correct design hierarchy. These guidelines can be used to help with partitioning the design:
Each team member module must be synthesized independently, creating a separate netlist to be implemented by the team member. This can be achieved with a bottom-up synthesis flow with a separate synthesis project file for each team member module. Alternatively, an incremental flow provided by Xilinx or third-party synthesis vendors can be used.
Good design partitioning greatly simplifies floorplanning. Each team member module is required to be constrained to a specific location in the FPGA using an area group region. This constraint prevents any placement conflicts during the assembly stage. During floorplanning, the following should be considered:
Team Member Synthesis and Implementation
Global Timing Constraints
All clocks in the top level should be constrained. All I/Os should also have timing constraints. Any top-level timing exceptions, including multi-cycle or false path, can be defined in this step.
The design directory structure must be defined so that each team member understands where the different files are located. The manner in which source control will be managed should also be defined.
The first implementation run should be carried out to verify the floorplan. For this run, the team member modules can be HDL, netlist, or a black box.
Team Member Projects
After the setup is finalized, each team member project or work space should be created. This can be done in the PlanAhead software or manually for a command line flow.
Team Member Synthesis and Implementation
After the initial setup is completed, each team member can synthesize and implement their portion of the design independently of other team member modules, but in context with the top-level design. The following flow choices are made during this step:
Each team member can iterate on their block as needed and periodically export results for use by the team leader in an assembly run.
At different stages in the design, the existing portions of the design can be assembled. This can be done at regularly scheduled intervals or when there has been a major update to one or more of the team member modules. When the assembly is done on a regular basis in the design stage, timing issues between modules can be found and fixed instead of finding major issues at the end of the design process. Assembly on a recurring basis also allows the team member to import the latest implemented version of other team member modules that are available after each assembly.
During assembly, the integrator (or team leader) imports any existing team member modules or uses black boxes if the design is not completed. The top-level logic, including routes between the modules, can be imported from the initial setup stage or implemented. For best timing, any logic in the top level should be implemented. There should be no placement conflicts during import, but routing conflicts can occur. These can be resolved by backing off the preservation level on different modules. Although the default value of the preservation level is to preserve both the placement and routing, it can be changed to preserve only the placement, allowing routing changes. For even more flexibility, the placement can also be changed. As a last resort, any module can be re-implemented.
The Team Design flow allows multiple developers to work in parallel on one design. This has several advantages:
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