The Challenges of Using Open Market IP In ASIC Designs Mohit Gupta Open-Silicon

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The IP ecosystem has evolved in recent years giving new dimension to some of the IP players in the semiconductor market. The never-ending debate on Semiconductor IP and whether to make or buy is still ongoing within some IDMs, but overall it has become clear buying at least some of the IP makes more sense than to reinvent the wheel. This strategy has been very successful when one considers the advantages:

• Better Time to Market: Using readily available IP can help kick start the chip design and ultimately leads to shorter design cycles.
• Reduced Risk: No need to prove the IP on internal test chips. IP vendors are likely to be early adopters of newer technologies and typically qualify the IP on their own test chip or in collaboration with a lead customer.
• Increased Focus: Companies can focus their R&D efforts on their differentiating technology, rather than spending their resources on designing IP, which often is standards-based and provides minimal differentiation to the end product.
• Lower Cost: Applying generic foundation IP like Standard Cells, General Purpose I/O libraries and Memory Compilers will often be cheaper as compared to the costs associated with internal IP development, verification and (test-chip) characterization.

Of course, one can argue that this approach has some disadvantages as well:

• Specification Compromise: "Off-the-shelf" open-market IP can never be fully optimized for all possible product applications. This provides a major challenge where criteria like area, performance and features may need to be traded off against aspects like cost, risk and time-to-market. Sometimes an in-between solution where available IP is customized by the vendor towards the customer-specific application can make sense however.
• No Ownership of IP: IP licenses come with various restrictions which can "get in the way". Examples are: re-use, disclosure and modification rights limitations which can possibly impair a company's flexibility if not taken into account well in advance.

IP Selection, Procurement, Qualification and Integration Challenge:

Procuring IP from third-party IP vendors looks to be a good option, but selecting and integrating that IP is rapidly becoming one of the biggest challenges in the SoC/ASIC industry. The success of an SoC depends on the careful selection of reliable IP which sufficiently meets the product's requirements. A significant portion of metal re-spins or redesign of chips is due to the fact that either the IP is not properly selected, or it has a bug inside or it is not properly integrated into the design.

To combat this, an IP selection and qualification process is needed. This process needs to be exhaustive and comprehensive and cover each phase of the ASIC design, from specification to GDSII. Even a small oversight, such as realizing late in the tapeout phase that one of the IPs uses LVt devices where only RVt devices had been budgeted for can have major impact on cost and schedule. A seemingly small mistake in the due-diligence as performed early in the ASIC development cycle, can lead to excessive costs down the road when the issue is encountered.

As part of the IP selection process, both compatibility and interoperability need to be insured. For example, in TSMC's 40G process, multiple voltages can be supported for the I/O oxide (1.8, 2.5 and 3.3V). However, not all combinations are supported at this technology node. The selection of different I/O libraries and PHYs needs to take this into account to ensure compatibility of the selected IP. Another example involves DDR PHYs and its associated controllers. Interoperability concerns can exist, especially in cases where the DDR and the PHY are procured from different vendors, as the standard for the interface between them is new and may, to a large extent, still be unproven.

At Open-Silicon we follow a very stringent IP selection, qualification and integration process, starting from day one when the project is still in the specification phase. Understanding customer requirements (or sometimes even driving them), selecting the right vendors, the right IP, conducting IP risk assessment and mitigation, as well as performing qualification and integration checks, are integral parts of any project that we execute. Each of these steps is composed of various checks and analysis in order to assure our customer and ourselves of one thing: The right IP is being used in the right manner!

Fig 1: Open-Silicon IP Selection and Qualification Process

It is very common for IP to be procured from multiple vendors. Working with each vendor requires careful management of technical, quality, business and legal issues. Taking hard-IP as an example, modern SoCs often integrate multiple high-speed serial interfaces, such as PCIe, USB, and XAUI; memory interfaces such as DDR; CPUs such as ARM, MIPS, and Tensilica; analog IP, including ADCs, DACs, PLLs, DLLs; and power management blocks, next to library and commodity IP that includes memories, I/Os, and standard cells.

Fig 2. IP Aggregation Process

At Open-Silicon, we have an automated incoming IP inspection process that helps us to find any issues with the IP very early in the project design cycle. The later a bug or an issue involving IP is caught, the more costly fixing it becomes.

Fig 3. Cost of fixing IP with design cycle

IP inspection encompasses checking the IP within itself and with the other IPs in the ASIC. When checking the IP within itself, we do checks related to IP compatibility with the technology process node selected in terms of mask layers, gate oxides etc. and IP compatibility with the used design flow. Checking the contents of IP delivery in terms of views completeness is another area that often gets missed. An agreement with an IP vendor might only cover basic views for the RTL to GDSII flow but there can be a requirement of specific views like IBIS models for IO libraries to do system level simulations which might come at additional time and cost. Also, there can be the case of an IP view/model having been generated using a flow from one EDA vendor, where it may not seamlessly work with another. Issues like these have the potential to negatively impact the project if not identified early.

Fig 4. Open-Silicon IP Qualification Process

IP Qualification also ensures that IP will work with other vendors' IP when connected to each other on the design. A sometimes-encountered scenario is the integration of a PHY/Serdes and controller from different vendors. Another area which requires attention when managing multiple vendors is the ESD compliance for the whole chip as IP vendors will guarantee ESD targets only for their individual IPs and have tested ESD compliance for the IPs only in their own testchip environment. At Open-Silicon, we incorporate specific ESD reviews and analysis for the various IPs integrated on a design to mitigate this risk during the Physical Design phase of the project.

Thanks to the incoming inspection process, we have seen significant savings in terms of last-minute ECOs and metal re-spins with the help of our IP qualification process by catching some of the issues very early on in the process.

Summary

Achieving a first-time-right SoC design more and more depends on IP selection, procurement, qualification and integration processes and methodologies that prevent the IP from possibly becoming the weak link in the chain. Ensuring that the IP as used in the SoC will ultimately meet all requirements is becoming a highly complex task that requires a dedicated, expert team with an explicit focus and responsibility to this task. Open-Silicon's IP experts work continuously with customers and IP vendors to identify market needs for IP with a special focus on early identification and development of IP to meet emerging standards.

The IP team works with a wide variety of IP providers and is continually qualifying and ranking IP and updating its portfolio of recommended IP. Primary goal is to help customers make informed IP decisions that differentiate their product, assure IP quality and reusability, and deliver first-time working silicon.

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About the Author

Mohit Gupta
Open-Silicon

Mohit Gupta is an IP manager with Open-Silicon, and is responsible for managing the IP for various networking, telecom, storage and consumer application programs. Prior to joining Open-Silicon, Mohit led teams at Infineon Technologies and ST Microelectronics where he was responsible for IP circuit design, layout design, characterization and quality assurance of IP. Mohit holds a BE Degree in EEC from Thapar University, India and an MS degree in Microelectronics from the Birla Institute of Science and Technology, Pilani, India. He also participated in the Executive Program in International Business Management from Indian Institute of Management, Calcutta, India.