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The Coming Impact of Mobile PCI Express (M-PCIe) on SoCs and Devices
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Moshik Rubin — Cadence

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The mobile devices we will use two years from now will be radically different from today's devices - and new system-on-chip (SoC) interfaces, particularly Mobile PCI Express® (M-PCIeTM), will enable them. While powerful, M-PCIe will introduce some design and verification challenges for SoC designers.

With worldwide unit sales of smartphones surpassing feature phone sales in 2013, and tablet sales continuing to boom at the expense of PCs, we might expect to see a period of stability since the mobile new world order has so clearly been established. Then again, perhaps no such stability will exist as today's mobile units morph into a new generation of more powerful and indispensible devices.

The driving forces behind this change are visibly at work. Convertible UltrabookTM/tablet devices attempt to deliver the convenience of tablets with the power of PCs. On the software side, Microsoft's Windows® 8 is the first operating system to combine touch with access to traditional business applications such as Microsoft Office. Though innovative, these convertible PCs continue to trail tablets in convenience, battery life, and consumer app support.

Tomorrow's mobile units will eliminate compromises by finally merging PC-class performance with the best features of smartphones and tablets. While processor and memory technology have been on a steady path to deliver that goal, critical infrastructure has been missing in mobile devices - most notably the backbone PC interfaces, USB and PCI Express. These interfaces must migrate to the mobile world to enable the massive ecosystem supporting them to be applied to mobile devices, and deliver portability and battery life with the power needed to run business apps as well as consumer apps.

The first important step in this direction occurred with the release of the SuperSpeed Inter-Chip (SSIC) specification in June 2012, which enabled USB 3.0 to connect chips within a mobile device using the low-power MIPI® M-PHY® physical interface. This makes it easier to leverage the huge USB hardware and software ecosystem in the mobile environment (the role of new USB standards in enabling Ultrabooks was described in an earlier Tech Talk).

A similar development has now occurred in PCIe with the newly announced M-PCIe specification. This specification combines the upper layers of PCI Express with M-PHY to bring PCI Express hardware and software functions to mobile devices.

With the release of this specification, the technology framework is now in place to enable development of the next generation of mobile devices.

History

The PCIe architecture is well known and one of the most successful and popular interface standards. MIPI M-PHY, however, is much newer and still being adopted by cutting-edge mobile devices companies.

The MIPI M-PHY specification realizes the MIPI Alliance vision: a single standard, powerful enough to address existing and future mobile devices requirements, and yet flexible and configurable enough to accommodate the low-power needs of diverse applications. That vision has been realized in today's M-PHY, but it took several years and two generations of standards to accomplish.

The first MIPI PHY standard, D-PHY, was introduced in 2005 and can be found on most mobile devices today. D-PHY is commonly used to connect an applications processor to a camera using the MIPI Camera Serial Interface (CSI). It is also used to connect the applications processor to the mobile device's display using the MIPI Display Serial Interface (DSI).

D-PHY's reach has not extended beyond the camera and display due to an inherent architectural limitation restricting the transmission rate to 1.5 Gbps. This was not seen as a limitation several years ago when the standard was conceived, but is simply too slow to handle the data traffic in today's smartphones and tablets.

To address the speed limitation, the M-PHY specification was written from scratch with a long-term outlook. This has resulted in a serial, low pin count, embedded clock PHY that offers multiple transmission and power-saving modes. The M-PHY supports data rates from 10kbps up to 6Gbps - enough bandwidth to support all types of data interfaces within a mobile device. Interfaces employing M-PHY now include several MIPI standards (CSI-3, DSI-2, LLI, UniPro, and DigRF), the USB SSIC standard, the Universal Flash Storage (UFS) standard, and now the M-PCIe standard. The interfaces are employed in a layered stack as shown in Figure 1.

Figure 1. Multiple Layered Interfaces Employing MIPI M-PHY

Integration Challenges

Integrating PCIe and M-PHY isn't a trivial task; a quick look at the PCIe state machine (Figure 2) shows the complexity of the protocol. Layering a different PHY underneath the existing PCIe stack required the resolution of several issues including mapping of M-PHY power states to PCIe states, error handling, and link discovery and configuration processes. These were just a few of the challenges that the dedicated PCI-SIG working group faced along with the requirement to maintain compatibility with PCI Express programming models.

 

Figure 2. PCI Express State Diagram

Design and integration of SoC blocks is always difficult, but designing the next generation of mobile SoCs incorporating M-PCIe interfaces will be especially challenging. Combining M-PHY, with its multiple configuration options, with the complexities of PCIe (as evidenced by its 1,000-page specification) could turn into a design and verification nightmare.

Cadence IP and VIP

In order to mitigate the risk of designing SoCs incorporating M-PCIe, Cadence has unveiled new IP and verification IP (VIP) products that support the M-PCIe specification. The first to be available commercially, these new products equip mobile SoC developers to get next-generation products to market quickly and with high quality.

The new M-PCIe IP, tapping into the family of Cadence® controllers and PHYs used across dozens of advanced PCIe designs, includes an enhanced PCIe controller with an M-PHY interface capable of supporting the M-PHY High Speed Gear 3 specification.

The new M-PCIe VIP, building on the proven Cadence Verification IP for PCI Express and the Cadence Verification IP for MIPI M-PHY, combines the upper layers of the PCIe Gen 3 protocol with the M-PHY physical layer. This VIP enables thorough verification of root complex and endpoint designs.

Together, the Cadence IP and VIP for M-PCIe can help speed the development of SoCs powering the next generation of mobile devices - devices which will incorporate the best qualities in today's smartphones, tablets, and PCs.

To learn more about Cadence IP and VIP for M-PCIe, see the links below and the Cadence announcement.

Cadence and the Cadence logo are registered trademarks of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners.

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About the Author

Moshik Rubin

Moshik Rubin is Senior Product Line Manager for Verification IP (VIP) at Cadence. He has been in the EDA industry for over ten years. He served as Verification IP Engineering manager at Verisity and now manages several protocols within Cadence's VIP portfolio including PCIe and MIPI verification IPs. Mr. Rubin holds a BS in Computer Engineering from the Technion - Israel Institute of Technology as well as an MBA from Tel-Aviv University's Recanati Graduate School of Business.