Craig Rawlings
Director of Marketing
Kilopass Technology Inc
As mask costs skyrocket for SOC designs on advanced process geometries, designers must develop new approaches for reducing multiple chipsets into a single SOC platform solution. Such a Platform SOC must support multiple product feature sets, interface variations, and individual feature functionality. Additionally, application-specific functionality can be configured through programmable firmware, firmware parameters, and configurable hardware, utilizing embedded non-volatile memory (NVM).
The primary market for Platform SOC architectures is consumer electronic products due to price sensitivity and segmentation by feature set to serve various price points in the consumer market, ranging from entry level features at the bottom up to the 'pro-sumer' features at the high-end. Furthermore, the same principles apply for industrial, medical, automotive, communications, defense, and high reliability space applications. As mask, design, verification, test, and operational NRE costs increase, the benefits of moving toward a Platform SOC architecture increase with broad applications in the semiconductor industry.
For the purposes of this article, a Platform SOC architecture is any semiconductor SOC architecture that encompasses in a single mask set what would otherwise require multiple mask sets. This indirectly implies that there exists some form of configurability or programmability after the SOC device has completed manufacturing. There are a number of valuable economic benefits derived from making Platform SOC feature sets and individual features configurable in post production.
A Platform SoC consists of a system-level solution consisting of multiple configurable functions integrated onto a single chip. These multiple functions can be configured to optimize the chip for various applications via programmable features integrated into the chip architecture. Thus a single Platform SOC can serve multiple market applications, with one chip design potentially replacing multiple SOC derivative designs that each requires a separate mask set. This directly benefits the SOC chip vendor in multiple functional areas.
Platform SOC Benefits
Since semiconductor engineering continually drives toward higher efficiencies and cost reductions within very tight design schedules, it only makes sense that the industry experiences an ongoing trend to make hard design become 'softer'. This results in immediate benefits including:
Reduced engineering risk
Longer product life cycles
Faster response to market changes
Decreased inventory risk
Reduced NREs
Enhanced Data / Code Security
Of course, an FPGA is the ultimate in Platform SOC architectures. Unfortunately, an FPGA also comes with a significant unit cost premium verses alternative semi-custom SOC solutions that continue to drive semi-custom and custom logic solution alternatives. As FPGA devices continue to improve in density and performance, and get adopted even in higher volume consumer applications, the advances of embedded programmable controllers, processors, and DSP IP has enabled ASIC/ASSP vendors to incorporate configurability into their design architectures in order to obtain FPGA-like benefits. Now with the availability of high density embedded non-volatile memory, ASIC and ASSP SOC architects are able to take more complete advantage of Platform SOC architectures in standard logic and mixed signal CMOS process technologies with many of the same benefits of a more expensive FPGA solution.
Methods for SOC Configuration
The scope of this article is to discuss some of the methods by which a Platform SOC architecture may be made configurable. In no way does this limit the imagination of the reader to go well beyond this limited discussion in the use of an embedded non-volatile memory block to derive diverse Platform SOC architectures with the end goal of consolidating multiple mask sets into one.
Specifically, Platform SOC architectures may incorporate configurable features and feature sets through various methods within a single monolithic chip that were previously impossible prior to the availability of embedded non-volatile memory technologies in standard logic CMOS. Several of these methods include:
Firmware storage in embedded NVM module
Firmware parameter storage in embedded NVM module
Digital tuning of analog or MEMS circuit(s)
Hardware configuration (e.g. MUX or Lookup Table)
As illustrated in Figure 1, SOC firmware and firmware parameters may be stored in an embedded NVM module. Since the firmware and/or parameters may be programmed depending on the specified system's requirements, only one SOC device is required for each combination of firmware image and parameter configuration.
Figure 1. Firmware & Firmware Parameters in Embedded NVM
In the case of programmable firmware parameters, depending on the system's firmware requirements, firmware parameters may be used to alter feature sets, limit available features for lower-end products, and modify specific system feature functionality. Having this capability within the SOC is critical for each chip vendor's SOC capability even though the SOC vendor's end customer may utilize off-chip NVM for extended features and functionality. There is an imperative that the SOC chip vendor tightly controls the firmware and any parameters for support and IP protection reasons.
As such, from the viewpoint of the SOC vendor, it is important that the embedded NVM technology restrict modification of either the SOC's firmware or its parameters through the availability of security or lock bits that prohibit such modification. As an extension of security related concerns, it is typical for hackers and competitors to attack security bits in order to hack or reverse engineer SOC devices. The highest level of physical security is provided only by standard CMOS antifuse based NVM technologies such as that offered by Kilopass' XPM (eXtra Permanent Memory). Notable security characteristics of a standard CMOS antifuse NVM are that the memory cell's state may not be detected through conventional de-packaging, de-processing, [FIB] voltage contrast, magnetic scan, or even cross section analysis.
Many Platform SOC architectures include requirements for some form of analog feature or feature set. The analog feature may be a type of tunable digital clock (MEMS), noise cancellation circuit, RF circuit, op-amp, sensor, LCD driver, or any other type of analog-to-digital interface within our analog world. Within the world of analog, the ability to tune, trim, and calibrate is primary to the analog circuit's functionality. Within the context of a Platform SOC with analog-to-digital features, the SOC architect may use on-chip NVM to limit operating ranges, disable or enable specific analog features, and provide varying degrees of measurement accuracy as indicated in Figure 2.
Figure 2. Analog Feature Configuration
As previously discussed, hardware configuration methods include methods for configuring both analog and digital circuit features. Since an embedded NVM module stores digital information, it may be more simply used for configuring digital logic. Traditionally, FPGA devices have configured logic functions through the use of multiplexer- or LUT (Lookup Table) based architectures. It is not necessary to use the same types of digital logic configuration methods in order to achieve powerful hardware configuration capabilities. With the advancement of deep sub-micron process technologies, logic has become extremely low cost. Therefore, there is a very low cost premium for building in a superset of digital logic features into a Platform SOC as indicated in a simplified view in Figure 3. Utilizing a simple programmable MUX or LUT-based architecture, a feature or feature set configuration may be programmed in post production. With sufficient planning and consideration by the system architect, this capability may be achieved at a fraction of the cost of an FPGA while meeting the design's low-power and high-performance requirements.
Figure 3. Digital Feature Configuration
Platform SOC Trends
While there has been little coverage, there is a very strong Platform SOC design trend that has been occurring in the semiconductor industry since the late 1980's. It started with the introduction of FPGA architectures that supported SOC logic and IO requirements. A number of FPGA families now include system analog features (such as phase locked loops, serializer-deserializers, and other functions). This Platform SOC trend is further evidenced by a movement in the ASIC world toward structured ASIC architectures. The benefits of moving device configurability into post-production are simply too compelling not to do it. In the ASSP world there are now replacement technologies for crystal clocks that enable designers to buy one clock device that may be tuned to different clock frequencies. The list goes on. All of these applications require non-volatile memory. Even the SRAM-based FPGA requires an external serial EPROM that stores the configuration pattern in order to function. Now with the availability of embedded NVM, all CMOS designers can enjoy these same benefits.
About the Author
Craig Rawlings has more than 15 years of experience in the semiconductor industry. Prior to joining Kilopass, Craig held management and executive-level positions at Hewlett-Packard, Actel, Resilience, and Progress Software. Kilopass is Craig's fourth early stage start-up experience. Craig's first start-up right out of engineering school was Cericor which was later purchased by HP. He was also part of the initial team at Actel and led that company's business expansion in the US, Japan, and Asia Pacific participating in Actel's subsequent IPO. Craig holds a B.S.E.E. degree and a Masters of Business Administration from Brigham Young University.
