Much has been debated in the press recently about the
future of the semiconductor intellectual property (IP) business
model. Among the issues cited as most dire are revenue models and
quality. Revenue models are directly linked to a company's long-term
competitive business strategy, and the ability to earn revenue and be
profitable in the IP business is obviously based on the quality and
performance of the IP.
It's clear that whether purchasing IP from a
third-party vendor or
developing it internally, there are inherent risks that result in
hidden costs. What often remains unclear is what and where those
hidden costs lie. For example, if a mask set re-spin is required due
to poor IP quality or performance, the average cost of a re-spin is
estimated at $1.3M for 90nm and $1.9M for 65nm, according to In-Stat
estimates. Based on industry acknowledged costs, the total IP
ecosystem cost is often more than twice the explicit cost of the IP
itself (Figure 1):
Figure 1. Hidden IP Costs
As a result, FSA has focused on developing tools that
enable the semiconductor supply chain to improve overall IP quality,
reduce the hidden costs within the IP ecosystem and improve IPs
manufacturability in semiconductor designs. More and more IP is being
outsourced than ever before, and designers are increasing their
reliance on third-party IP to solve complex design
problems. Simultaneously, increasing complexity is complicating
transactions, making IP more difficult to integrate and
support. Although the availability of third-party IP is critical to
the continued growth of the outsourced business model, there are many
aspects about IP that remain problematic.
There are explicit and hidden costs throughout the ecosystem,
especially at interface points between different groups and companies,
which becomes more challenging as IP core performance and complexities
increase and as process technologies advance.
FSA believes the outsourced ecosystem can reduce the total cost of IP
integration through structured, low-cost IP qualification. This
includes establishing risk profiles and modeling techniques for IP and
IP functionality in designs.
To address this concern, FSA has developed an IPecosystem™ Tool
Suite, designed to provide engineering and business guidance for hard
IP risk assessments. The goal is to provide companies purchasing IP
with a more efficient means of integrating and utilizing IP.
FSA's IPecosystem™ Tool Suite enhances a company's internal capability
by enabling the creation of a best practices approach to define a
strong communication link between the IP vendor, integrator and
foundry. It provides a base set of questions that enable information
exchange under a password-protected and a secure encryption
methodology between IP vendor and integrator and integrator and
foundry to produce a risk profile at the four major IP junctures:
pre-purchase, licensing, technology and manufacturability risk
assessment.
The tool assumes information is exchanged between companies under a
non-disclosure agreement and is designed to be used as part of a
broader evaluation of IP, rather than to be used exclusively in making
a final decision.
FSA's Hard IP Quality Risk Assessment Tool, the first tool introduced
in the Suite, consists of a set of questions for categories of IP
interaction that communicate the quality aspects of an IP core, and it
develops a risk profile for integrators to evaluate the quality of the
IP. This can be applied to its original focus of third-party IP, or
can be used for evaluating internally developed IP for reuse in other
designs. In addition, it allows both integrators and vendors to
compare all of their IP to an industry best practices baseline for
quality.
The Tool has been built around a workflow process, allowing for
flexibility and customization. The Tool gathers information about an
IP vendor's design methodology, foundry qualification and details
about specific IP. The questions are focused on IP families, making it
less time-consuming for the vendor to complete and easier for the
integrator to weight specific factors.
By answering a series of questions, the integrator can generate a risk
profile that focuses on seven categories for evaluation. These include
(Figure 2):
IP Design
IP Integration
IP Verification
Process Technology
Product Documentation
Reliability
Test
Figure 2. Risk Profile Example With Seven Categories
FSA is pleased to announce version 3.0 of the Hard IP
Risk Assessment Tool today. Version 3.0 includes a number of
enhancements, most notable being the partnership between FSA and Chip
Estimate, who will carry the tool on its website to freely allow
integrators and IP vendors to seamlessly request and communicate the
risk profiles globally and effortlessly. Key enhancements making the
biggest impact in version 3.0 include:
Custom Questionnaire - A custom questionnaire has been added that
allows vendors to add unique questions pertaining to specific IP.
Likewise, the integrator can ask questions of the vendor. Those
questions can also be weighted for specific factors. This is a
valuable benefit to vendors, as it allows them to emphasize qualities
about a specific IP family to an integrator. Integrators benefit from
the additional due diligence they can perform by asking customized
questions for their intended usage.
Answer Verification - A new filter has been added to the
Integrator's Hard IP Summary page, allowing an answer to be verified. This new
feature makes it easier for vendors and integrators with long-term
relationships to add a yes/no confidence level, which is reflected in
the bar chart.
Feedback Button - The feedback loop has been enhanced, allowing
integrators to provide detailed feedback directly to the vendor. It
also packages the risk profile and Hard IP Summary with custom
weightings with the feedback, These enhancements will
be quite valuable in aiding the vendor for additional improvements to
its IP.
Chip Estimate Collaboration - FSA has collaborated with Chip Estimate
to bring greater value to the industry with its IPecosystem™ tools. Vendors
now have an option to upload their Hard IP Quality Risk Assessment
Tool risk profiles to Chip Estimate's IP portal (Figure 3). In
addition, Chip Estimate users will have the option to request a
vendors risk profiles or request that a vendor complete the FSA Hard
IP Quality Risk Assessment Tool for their IP or family of IP within
their portfolio.
Figure 3. View of FSA's
Hard IP Quality Risk Assessment Tool on ChipEstimate.com's portal
The second tool in the Suite focuses on Licensing. It has been
documented that the IP licensing period can take up to 22 weeks. This
new industry tool will shorten this time period by creating
efficiencies for IP purchasers. It features a set of questions that
every integrator needs to ask to understand the IP licensing risk
before entering into a licensing agreement. Licensing will be included
in version 4.0, planned for delivery by November 2007.
The Quality and Licensing tools focus on selecting an IP vendor based
on evaluating the quality risk involved with various IP offered and
then moving to the licensing process to assess the licensing risk an
integrator is willing to accept before acquiring the desired IP.
The Technology and Manufacturability tools will focus on identifying
the risks involved with producing a design with the acquired IP at
various nodes with different foundries. These two efforts will
initiate on September 12, 2007 at FSA's Supplier's Expo at the IP
Subcommittee meeting at Santa Clara Convention Center at 12:30pm
(Great America Meeting Room 2). Everyone is welcome to participate.
The Technology tool will feature a set of questions that focuses on
PDKs, models, lithography and OPC issues, etc. to determine the
technological enablement and readiness of the IP under evaluation.
The Manufacturability tool will feature a set of questions that
identifies a risk profile to ensure the chip designed with the IP will
manufacture at yield in a timely manner at the lowest possible cost.
As the leading semiconductor association focused on the outsourced
business model, FSA represents the entire outsourced design ecosystem
for semiconductors from fabless companies and IDMs to IP and EDA
vendors to foundries, packaging and test, and many others. FSA's
mission is to accelerate the growth and increase the return on
invested capital of the global semiconductor supply chain by promoting
an environment for innovation. FSA accomplishes this by identifying
and articulating industry challenges and providing a non-competitive
platform for collaboration between these ecosystem partners to
identify solutions.
This mission serves as the motivation for creating and giving this
IPecosystem™ Tool Suite to the industry free of charge without
licensing agreements and without desire to influence transactions
between various players in the industry. It is a means to educate,
address the IP challenges proactively and positively, and improve the
invested capital in the semiconductor ecosystem globally.
With FSA since January 2001, Lisa Tafoya serves as
FSA's Vice President of Global Research. She brings more than 16 years
of experience in market research and marketing communications to her
role in FSA. Ms. Tafoya performs the strategic planning and oversees
the implementation of all FSA reports, surveys and deliverables. She
oversees all data collection and analysis, as well as global
publications created and distributed by FSA. In addition, Ms. Tafoya
is responsible for FSA's subcommittees worldwide, managing their
strategic focus and overseeing the deliverables, including FSA's
IPecosystem™ Tool Suite, MS/RF Spice Model Checklists and PDK
Checklists, as well as the Standard Foundry Process Qualification
Guideline (now a standard under JEDEC), as well as researching and
addressing technology and business challenges in the semiconductor
industry. Ms. Tafoya is also co-author of an FSA book, Understanding
Fabless IC Technology, published by Elsevier Publishing in 2007.
