EFFECTIVE ESD STRATEGIES IN NANO-CMOS IC DESIGN

By Katty Van Mele
Business Development Manager
Sarnoff Europe

The hunger for shorter design cycles and rapid product innovation needs to be fed by a.o. silicon and product proven re-usable IP. To address such important business need, Sarnoff Europe introduced so-called TakeCharge® Design Kits, offering proven solutions with design and integration tools for on-chip ESD protection, which is another non-core but necessary technology for nano-CMOS ICs. The response from foundry and fabless companies worldwide reflects the importance of integrated ESD design in the overall IC design process.

Trends and Challenges for ESD design in 65nm

Until recently, IDM companies were leading the new technology and application introductions, preceding the industry by an entire process generation. However the fabless/foundry industry caught up with the IDM market in terms of product innovation, new supporting platform alliances, and also enticed them to fab-lite business models.

Moreover, the fast increasing complexity of innovative IC design prompts the use of advanced 3^rd party IP. Fast ramp-up of new IC, together with a vast array of additional functionalities that are implemented with each new product release, necessitate the integration of IP which can be used on multiple processes and foundries.

The increased competition in the fabless design sphere has made differentiation and innovation in the IC design the ultimate key to success. Standard application CMOS ESD design down to 180nm was generally covered by foundry process rules, with little need for additional expertise. The introduction of advanced nano-CMOS IC design has changed the scope of ESD design into an integral part of innovative IC design.

Advanced ESD design has become an enabler of IC design differentiation and innovation. All too often, the ESD design concepts implemented successfully in mature process generations compromise IC functionality when applied in 65nm IC design. At the same token, too many innovative IC's fail to make a timely entrance in the market due to ESD failures. "Today, more than 25% of the fabrication failures and 38% of the field returns are attributed to EOS/ESD" said M. Mergens at an ESD web seminar in October 2007. "It is the predominant failure mechanism for ICs."

Companies are increasingly faced with the difficult choice between meeting ESD specs or meeting the product release deadline. And yet, even in nano-CMOS, ESD design should never become such a critical issue.

The requirements for adequate ESD protection have kept pace with the increased IC design complexity, and the solutions must fit advanced custom design applications. However, economic pressures, the cost of nano-CMOS IC design and the need for fast ramp-up of production, now also require the design teams to prepare their IC design for production on different fabs and/or foundries. In order to successfully design ESD protection strategies in this changing process environment, the IC designers now need to implement process independent ESD solutions, often prompting the need for a total review of in-house ESD experience and expertise.

To top off the challenges, since in-house ESD teams become fully involved in the IC design flow in order to integrate adequate ESD protection strategies, this reduces their window to develop such advanced ESD solutions, while their need for specialist expertise increases. Many companies have replied to this challenge by adding 3^rd party ESD IP to the in-house knowledge. In-house design teams can tailor this additional and highly specialized IP to their specific individual IC design needs while preserving the unique nature of their individual design. Nevertheless, they can rely on product proven ESD solutions and strategies and ensure multi-fab manufacturability of the design, without considerably increasing the cost of ownership.

TakeCharge® advanced ESD solutions : empower the IC designer - enable the IC design

Sarnoff Europe has built up an extensive solutions portfolio focusing on such advanced and specialty applications as high speed, SerDes, RF, analog and mixed signal design. These applications require highly specialized and/or scalable ESD protection concepts to adequately protect custom innovations. ESD solutions are product proven down to 65nm on multiple foundry and proprietary processes, while silicon analysis is currently being carried out on 45nm solutions.

As IC design moves into advanced nano-CMOS space, Sarnoff Europe has continued to focus on the smallest possible protection concepts, ensuring lowest capacity and resistivity for applications in high speed / SerDes interfaces (e.g. HDMI, DVI,...), communication and networking environment, logic LSIs (FPGA, Asic, ...), LCD driver IC, power management ICs or applications on SOI technology. Based on its experience in these different types of applications, Sarnoff Europe has built up a reputation for its specialty ESD solutions, backed up by more than 335 advanced volume products to date in which TakeCharge® ESD solutions are implemented.

Moreover, the company focuses heavily on the individual design needs of innovative design companies. Sarnoff not only licenses a set of process/foundry optimized solutions, but also delivers a full package of ESD design strategies and methodologies, integration and calculation tool in the TakeCharge® Design Kit, available for all major foundry processes and generations in standard nano-CMOS, or custom made for proprietary and/or specialty processes such as HV-CMOS, SOI....

As an IP provider, Sarnoff Europe focuses heavily on design enablement. TakeCharge® customers are empowered to independently implement the solutions and protection strategies into their IC design, without the need for constant consultation throughout the design cycle. To empower the ESD/IC design teams, the TDK includes mandatory a 2-day training, with full Q&A period and first product ESD review by Sarnoff engineers prior to tape-out. In 2007, 130 new products were successfully released by customers, underlining yet again the versatility of Sarnoff's ESD solutions.

Case study : TakeCharge ESD solutions for communication and networking applications

Background

Recent applications require higher signal data throughput than ever before. PC (Serial ATA, PCI-express) and multimedia (DVI, HDMI) interfaces are running at speeds between 1Gbps and 10Gbps. At these data rates, the IO designer must carefully define the matching circuit connected at the bond pad. Impedance variations can cause reflections and ringing. Signal attenuation and degradation can cause the characteristic 'eye' measurement to close at the high frequencies. Many of these high speed interfaces rely on serial communication using differential LVDS or TMDS circuit concepts to channel the multimedia content between set top box, DVD player and TV receiver sets.

ESD complexity

To create economically viable circuit solutions, IC designers rely on standard digital (foundry) CMOS for the multimedia applications. However, the advanced CMOS process nodes (130nm - 90nm) include sensitive elements that are easily damaged during ESD stress. Certainly for the HDMI, DVI interfaces where the end user interaction can cause severe system level stress, robust and effective ESD protection must be in place. While many system makers relied on board-level ESD protection in the past, today most are working to include the ESD protection on-chip, requiring 8kV HBM (Human Body Model) protection.

Adding ESD protection onto the silicon die, adds parasitic capacitance to the IO pad which can possibly degrade the signal at higher frequencies. IO designers need low and stable (over signal voltage and frequency) capacitance and low resistance. Also the leakage of the ESD protection cell must be limited because many of the Consumer Electronics appliances are powered from a battery.

Experience from Sarnoff

Sarnoff has been working together with a number of customers (Fabless and IDM) in the field of high speed IC applications. Currently product proven solutions for the following IC applications are available on the market

Key technical benefits for working with Sarnoff

IC designers have worked with Sarnoff to enable high speed throughput without compromising interface ESD performance.

For high speed interfaces, Sarnoff has focused on multiple items:

• Area efficient ESD solutions to reduce the total ESD area as much as possible.
• Low capacitive, low resistive
• High ESD protection with low cap: 100fF-200fF for 4kV
• Low-to-zero resistance in the pad
• Scalable ESD performance to allow any ESD requirement on-chip.
• Low leakage and Latch-up immune devices
• Over voltage tolerant options available

Example circuit protection

An example of a protection concept for a SerDes application in 90nm is depicted below. The end user required 200V Machine Model (MM) on-chip ESD protection.

Customer testimonials

• Bradley Howe, vice president of IC Design at Altera,
• "We chose TakeCharge® technology for our FPGA product families as part of Altera's commitment to deliver high-performance, cost-effective programmable products to our customers. TakeCharge® has allowed us to effectively manage both ESD protection and IO area."
• Shoji Ichino, general manager, Technology Development Division, Electronic Devices Business Unit of Fujitsu Limited
• "Fujitsu selected Sarnoff's TakeCharge® to help continue our tradition of providing customers with highly reliable high-performance products and services based on powerful technologies. TakeCharge® will be Fujitsu's primary ESD solution for their 65nm CMOS technologies after its full deployment in Fujitsu's related standard IO libraries."

Sarnoff Europe headquartered in Gistel, Belgium, is a subsidiary company of Sarnoff Corporation, formerly known as RCA Laboratories. Sarnoff Europe assumes worldwide responsibility for the development and commercialization of Sarnoff's TakeCharge on-chip ESD protection IP.

Search for Sarnoff Europe ESD IP here.

About the Author

Katty Van Mele joined Sarnoff Europe in 2006 as Business Development Manager, bringing more than 15 years experience in worldwide B-2-B marketing and business development in several technology sectors with her. In this position, she has been responsible for expanding the fabless partner base both in the North-American and Asian markets. Moreover, she actively fostered new alliances with top-tier foundries such as UMC, Tower Semiconductor, ...

Prior to joining Sarnoff Europe, Katty held positions in business development and strategic alliances with Citilog and Traficon in Europe, and with the Dynamic Holding Group in Hong Kong/China. She received a post-university degree in International Economics/Relations and East-Asian Economy from SAIS, The Johns Hopkins University.