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1T OTP Memory: Delivering Quality and Reliability

By Wlodek Kurjanowicz
Founder and CTO
Sidense


Introduction

Today's consumer electronic and wireless markets are under heavy pressure to reduce costs, increase performance, minimize power consumption and increase security.

Configurability and programmability, which is accomplished with one-time programmable (OTP) memory, becomes the key enabler to achieving these goals. OTP addresses such usages as redundancy and option select, coefficient storage, analog trimming, RFID and chip ID, boot code, firmware and secure encryption key storage (such as HDCP keys for HDMI).

What is needed is an area-efficient, low-power, high-performance and highly reliable OTP memory that helps consumer electronics and wireless manufacturers reduce costs, serves their high density and high performance code storage requirements and ensures that encryption keys are securely stored. The answer to this requirement is Sidense's unique, patented, single transistor (1T) antifuse 1T-FuseTM OTP memory, which offers higher performance, density and reliability than any alternative NVM solution.

This paper examines 1T and 2T/1.5T (two transistor) OTP memory cells and explains why Sidense's 1T cell is significantly more reliable than any of the alternative multi-transistor antifuse devices.

A Brief History of Antifuse

Antifuse technology has been employed by the semiconductor industry for over 25 years. An antifuse is defined as an electronic device that changes state from not conducting to conducting or from higher resistance to lower resistance in response to electrical stress (a programming voltage or current). Initial antifuse inventions focused on a capacitor blown between crossing conducting lines (1969). An MOS gate oxide breakdown antifuse was invented by Texas Instruments in 1979.

In 1982, a dual-gate-oxide two-transistor (2T and 1.5T) MOS antifuse was introduced, leading to what has become a viable OTP embedded memory architecture. Since the adoption of a dual-gate-oxide technology (3.3V/1.8V) in 0.18um technology, MOS antifuse has become available in a standard CMOS logic process which does not require any additional masks or processing steps.

Subsequent advancements in CMOS technology, however, posed new challenges and barriers to the classic 1.5T antifuse architecture: density, reliability and portability between fabs. 1.5T memory cells do not scale well with process. Reliability is compromised by tail bits in the programmed cell current distribution. Portability between fabs is limited by high cell sensitivity to drain engineering.

Sidense's patented 1T-Fuse architecture overcomes all the aforementioned issues, paving the path for reliable, standard OTP solutions in advanced CMOS technology nodes. Sidense's patented split-channel memory cell scales well with process, does not suffer any dependence on drain engineering and is the only single transistor OTP solution in the industry that does not require any additional masks or processing steps.

1.5T Cell Reliability and Programmability Concerns

The cross section for a classic 1.5T antifuse cell is shown below in Figure 1.

1.5T Antifuse Cell figure

          A Classic 1.5T Antifuse Cell

Figure 1. A 1.5T bit cell can experience oxide breakdown (program) in three different regions, resulting in a multi-modal distribution of programmed cell current with tail bits compromising programmability and reliability.

As can be seen in Figure 1, programming of the 1.5T cell is not well confined in the channel region. In fact, the 1.5T cell can program (experience oxide breakdown) in three different regions: (1) the channel region, (2) the leakage control (pocket or Halo) ion implantation region, and (3) the LDD diffusion extension region. This results in a tri-modal distribution of the programmed cell current and is very susceptible to large tails in the current distribution.

Breakdown to the LDD region (3) forms a resistive link between the n+ polysilicon and the n+ diffusion, resulting in a high current tail. Breakdown to the channel region (1), which is the dominant mechanism, forms a diode-connected NMOS transistor characterized by a particular threshold voltage and resistance. Breakdown in the pocket or Halo region (2), which has a higher p+ concentration, results in higher resistance or higher Vt, leading to a low current tail.

Tail bits compromise reliability and programmability

The tail bits in the multimodal distribution make the program verification process extremely difficult and error prone. The cells programmed in the Halo region (2) might be weaker than the partially programmed or leaky cells in the LDD region (3). Since the partially programmed cells should be eliminated, as they can heal with time, the program and verification conditions must be experimentally optimized for each process and each fab. This leads to a compromise between reliability and programming yield.

Self healing of the partially programmed cells

If the read reference is adjusted to read weakly programmed bits, on the order of 1uA, a cell that has not yet been fully programmed but shows increased tunneling leakage current (>1uA to LDD), which is the first stage to oxide breakdown, may be incorrectly classified as a programmed cell. The charge, which is trapped in the oxide and is responsible for the leakage, can eventually be removed during device operation lifetime resulting in "self healing" and poor device reliability since the cell will no longer be viewed as "programmed".

Higher read voltage limits retention

The low current tail bits require higher read voltage and/or longer read time, both of which increase exposure of the un-programmed memory cells to the elevated voltage during every read operation. This shortens the total memory retention time according to TDDB curves for the gate oxide.

Portability limited by the LDD process dependence

Direct exposure of the gate to the diffusion edge in the 1.5T cell results in strong sensitivity of the cell to drain engineering, limiting portability between fabs.

Since the LDD technology details (pocket or Halo implantation) are manufacturing-equipment specific, the 1.5T qualification must be repeated not only for every node, but for every fab in a given process within the same foundry. Qualification should also be repeated if any process improvement has been made to the NMOS transistor.

1T OTP - Delivering Controlled and Reliable Programming

Figure 2 shows the cross section of Sidense's patented single transistor antifuse cell (1T-Fuse), in which reliable and repeatable programming is entirely contained to the channel region. This novel memory bit cell scales well with process and does not suffer any dependence on drain engineering. It is the only single transistor OTP solution in the industry that does not require any additional masks or processing steps.

Sidense's Patented Split-Channel Cell

1T-Fuse bit cell figure

Figure 2. The 1T-Fuse bit cell is a two-terminal, split-channel device that looks like an MOS capacitor in the un-programmed state and a diode-connected MOS transistor in the programmed state. All programming occurs in the transistor's channel region for high reliability and repeatability.

The 1T-Fuse cell uses a patented split-channel, variable thickness gate oxide manufactured in a standard-logic CMOS process with no additional masks or process steps. The gate oxide underneath the polysilicon gate consists of both thick and thin oxide regions, where the thin oxide is used for programming (breakdown). This area-efficient and highly portable design has been verified in a wide range of process nodes from the leading foundries including 180nm, 130nm, 110nm, 90nm and 65nm.

Figure 3 compares the programmed cell current distribution for 1T and 1.5T cells manufactured on the same chip and programmed and tested under identical conditions. As can be seen in these histograms, the cell current for the 1T cell is well controlled and contains no tails in the distribution. This is contrasted with the 1.5T cell, which produces large tails and, as explained earlier in this paper, leads to quality and reliability issues.

comparison of multi-modal distribution of programmed cell current for a 1.5T cell and repeatable cell current of a 1T cell graph

Figure 3. This graph shows the multi-modal distribution of programmed cell current for a 1.5T cell as contrasted by the well contained, repeatable cell current of a 1T cell.

Improved Yield and Reliability

Absence of the large tails in the 1T cell current distribution allows for better program verification control, along with improved programming yield and reliability.

The 1T bit cell's reduced size results in higher yield and lower product costs for OTP customers. Additionally, since oxide defects are directly related to area, the smaller 1T cell inherently provides greater quality and reliability than a 1.5T or 2T cell.

Lower Power and Higher Performance

In addition to improved density and reliability, the 1T-Fuse cell enables significant power reduction and speed improvement.

Sidense's Low Power (SLP) architecture targets RFID and other ultra low power applications such as medical implantable devices. Additionally, the sub-10ns Sidense SiPROM architecture is the fastest embedded NVM solution in the industry.

The Clear Choice

With the smallest cell area, fastest access time and the lowest power consumption, Sidense 1T OTP provides significantly better reliability and programmability than any alternative NVM solutions. Sidense 1T OTP is the clear choice for today's consumer and wireless markets.

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About the Author

With over 25 years of IC design and manufacturing experience, Wlodek Kurjanowicz has led numerous design, design automation and design analysis groups. In 2003 he founded Sidense Corp. with a vision to build a reliable NVM solution for sub 100nm CMOS technologies. In 1998 he co-founded ATMOS Corp., the embedded memory IP company, which he lead as its Chief Technology Officer to become the world leading provider of embedded DRAM compilers. Wlodek became a Mosys Fellow following the ATMOS acquisition by Mosys Inc. (Nasdaq: MOSY) in 2002. Prior to that, he managed the Design Analysis Group and held the position of Senior Technical Advisor at Chipworks, and was a Member of Technical Staff at Semiconductor Insights Inc. He also held various IC Design Manager and IC Technology Manager positions in a Polish semiconductor plant. He holds six patents in addition to several pending applications in the memory IP space.


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