PFI Low-Power Design Guide
Details Methodology and Design Examples Using
the Common Power Format
By Susan Runowicz-Smith
Group Director
Cadence Design Systems, Power Forward Initiative
With gas prices at record levels and
the effects climate change in almost every headline, reducing energy
consumption is on everyone's mind. From the chip designers' perspective,
global warming and the price of electricity manifests itself as a chip
power management challenge. At the same time that customers are demanding
cheaper, energy saving electronic products, chip designers are now faced
with power density challenges when adopting advanced CMOS process geometries
at 65nm and below. The traditional IC design and manufacturing infrastructure
has been built largely to address performance and area (silicon cost)
targets and only treat power consumption as an afterthought. Cheaper
electronics often were derived by a move to smaller silicon process
geometries. Focus has been instead on running circuits at the fastest
possible processing speed to deliver the best possible performance within
the smallest silicon. With shrinking geometries below 65nm, power consumption
must be an equally considered design constraint with new approaches
adopted to minimize power consumption while maintaining functionality,
cost and performance. As designers attempt to implement advanced power-lowering
design techniques, limitations in design infrastructure become apparent.
These limitations have prevented companies from initiating low-power
design projects in advanced technology nodes due to high levels of chip
failure risk and unpredictable design costs.
The Power Forward Initiative
Fortunately, leaders across the IC design
and manufacturing chain have recognized the need to address power in
a holistic way across the silicon design chain so that power can be
considered equally along side performance and area. To solve the broad
design infrastructure problem, required involvement of the entire electronic
product development design chain, including systems and EDA companies,
IP suppliers, foundries, ASIC and design services companies. In May
of 2006, Cadence teamed up with 9 other industry leaders - ARM, AMAT,
AMD, ATI, Freescale, Fujitsu, NEC Electronics, NXP and TSMC-- to form
the Power Forward Initiative (PFI). PFI's collective aim is to link
design, verification and implementation to reduce risk and increase
predictability in chip power reduction. Members have worked to adopt
a new automated design infrastructure based upon the Common Power Format
(CPF) that is aimed at reducing chip power consumption while minimizing
the risk in adopting a new more automated power-aware design methodology.
The founding members of PFI worked together
to refine and validate a holistic, CPF-enabled
design, verification and implementation methodology. From the very outset,
the goal was to quickly enable the rapid deployment of a design automation
solution that comprehends power at every stage of the design process.
Today, that CPF-based infrastructure has been deployed; its adoption
is growing rapidly and producing successful energy saving chips worldwide.
PFI History
Starting in 2006, the founding companies
of PFI reviewed and refined the CPF specification.
They then initiated proof point projects that validated design flows
using the Cadence® Low Power Solution with complex designs and power
intent for these designs specified in CPF. By the fall of 2006, the
PFI membership grew to nearly twenty companies. The ecosystem's desire
for a comprehensive low-power solution was evidenced by broader support
of CPF across the design chain. Complex low-power design projects were
underway at nearly all of the founding PFI member companies. IP companies
began incorporating CPF into their implementation flows and leading
foundries were busy readying reference flows based upon CPF-enabled
methodology.
PFI members completed their work on the
CPF specification in late 2006 and determined that CPF was ready for
broad deployment and standardization. The CPF specification was contributed
to the Silicon Integration Initiative (Si2)
Low Power Coalition (LPC) in December 2006.
In March 2007, after working through the LPC process, CPF 1.0 became
a Si2 standard, freely available to everyone in the industry.
During the two years that the PFI members
have been working on refining and validating a CPF-enabled design methodology,
a wealth of experience has been gained in the effort. PFI Members shared
their design and methodology experiences at quarterly meetings, industry
conferences and other public forums. At each meeting, those participating
were impressed with the progress in bringing CPF-enabled methodology
to the design community so quickly. CPF-enabled methodologies have
been developed, refined and proven to not only reduce energy consumption
but also dramatically reduce the time it takes to design and verify
low power chips. It was clear now that our next project must capture
this experience of the PFI members in one place for the global design
community to share.
PFI Low-Power Design Guide
Pioneering work of the Power Forward
Initiative members has resulted in A Practical Guide to Low Power
Design - User experience with CPF. The Guide embodies the collective
intellectual work and experience of some of the best engineers in the
electronics industry. The methodology was developed and refined by users in close collaboration with tool and IP providers, Foundry
partners and the entire silicon design chain. It focuses on practical
design issues and address real-life design challenges including how
to take advantage of advanced low-power design techniques-such as
power shut-off, and dynamic voltage and frequency scaling-and describes
how these techniques have been automated to ensure correct functionality
and rapid design, verification and implementation.
Available free of charge from the Power Forward Initiative, the guide is divided into six sections: Introduction
to Low Power; Verification of low-power Intent; Front-end Design; Low-Power
Design for Test; Low-Power Implementation; CPF User Experiences; and
CPF Terminology Glossary. User experience chapters capture early design
experiences including chips that have been manufactured in silicon from
Freescale, Fujitsu, NEC Electronics, NXP and Faraday Technologies. Other
chapters are included from leading IP companies ARM and ARC International
that outline silicon validated (ARM), CPF-enabled, low-power versions
of their commercially available IP. A chapter from TSMC outlines their
CPF-enabled Reference Flow 8.0 and Sequence Design describes its industry
first Early Power Analysis with CPF. The guide illustrates the results
of PFI members' collaboration to accelerate the adoption and deployment
of CPF-enabled design flows. It is published on-line and will be regularly
updated to include more easy-to-read examples that can help designers
get started reducing power consumption on their next design project.
Susan Runowicz-Smith joined Cadence in
2002 following the acquisition of Simplex Solutions. As Business Enablement
Group Director, she has been instrumental in driving industry-level
initiatives including the Silicon Design Chain and the Power Forward
Initiative. During her 20+ years in the EDA industry, she has wide ranging
experience in business development, product marketing and EDA tool development
at Simplex Solutions, Synopsys, LSI Logic, Zycad, Schlumberger and DEC.
She received her B.S. in Applied Mathematics from the University of
Massachusetts at Lowell.
