By Dan Hillman
Vice President of Engineering
Transmeta Corporation
Advanced process technologies (90nm, 65nm, 45nm and below) pose difficult power management challenges for chip designers. Exponential growth of leakage power can result in unacceptable increases in total power (leakage + dynamic), and standby power. Manufacturing variations can result in a wide distribution of minimum frequency and maximum power consumption across parts. Wide process distributions can prevent parts from achieving acceptable yields within a given power and frequency specification. Chip designers are challenged to choose between a standard process to meet performance goals or a low power process to meet total power or standby power goals.
LongRun2TM Power Management Approach
Transmeta’s LongRun2 technology addresses these challenges with a comprehensive solution that includes: hard IP advanced algorithms, innovative circuits and manufacturing optimization methods.
LongRun2 technology is a suite of IP based post-wafer-processing compensation, power management, and leakage control technologies that optimize leakage power and diminish process variations in designs. LongRun2 offers a solution to meet performance, dynamic and static power. LongRun2 technology can dynamically adjust Vt and Vdd to selectively reduce the effects of process variation to improve yield, reduce worst case power at a given frequency, or increase performance within given power limits
Process Variations
Most design parameters that chip designers use are subject to a statistical variation, often resembling a normal (Gaussian) distribution. Semiconductor foundries provide parameters to chip designers to account for the statistical variations in their process, outlining the fastest and slowest transistor speeds in their process. Because there are two types of transistors in a CMOS process, the NMOS and PMOS transistors, foundries provide the values that form the four different corners and the center of a “SPICE Box” – denoted as fast-fast (FF), slow-slow (SS), fast-slow (FS), slow-fast (SF) and typical-typical (TT). A “SPICE Box” is illustrated in Figure 2. The impact on design leakage from the SS corner to the FF corner can be as much as 30:1.
Typically, parts designed for a fixed supply voltage and manufactured in the FF corner will have the highest frequency, have the most leakage (which sets the power specification) and provide the best performance. Similarly, parts manufactured in the SS corner will have the slowest performance (which sets the speed specification), have the least leakage and consume the least power.
Tightening the SPICE Box
Threshold voltage control can be achieved with a technique called body bias, also known as back bias or substrate bias. Body bias leverages a MOS transistor effect known as the ‘body effect’ to control Vt. As shown in Figure 1, the application of reverse body bias raises the Vt of the NMOS and PMOS transistors. The overall effect is to take the FF, FS, and SF points of the SPICE box and move them closer to the SS corner. This technique works on all Vt variations, low, standard and high, within a process node. This can be a post-process adjustment performed on packaged parts, or alternately a new library corner could be made at the FF corner with bias applied. In the latter case, the chip designer can take advantage of the improved SPICE box to realize a lower power design. For example, a 30:1 leakage variation can be reduced to 5:1 with the use of reverse body bias. The amount of Vt change, and therefore leakage reduction, resulting from reverse body bias is called tunability. The amount of tunability in each process is different. Figure 1 – Tightening the SPICE BOX with reverse body bias
Figure 2 shows two graphs, one with Vt distribution and one with power distribution, that illustrate two yield curves – one without threshold voltage control (No LongRun2), and one with threshold voltage control (LongRun2). With reverse body bias the threshold voltage is increased which lowers the leakage power and performance of the circuit. The curve on the left shows the shift in Vt distribution with LongRun2. And the curve on the right shows the static power reduction as a result of the Vt shift from LongRun2. The LongRun2 curves show the improved parts distribution to a newer lower power specification and tighter distribution. Note that the threshold shift is not large enough to affect the circuit performance. Figure 2 – Improved Vt Distribution and Power Specification with LongRun2
Production Proven Technology
The LongRun2 technology has been proven to work effectively in volume production on NEC’s M2 mobile phone chip. LongRun2 and other power reduction techniques were used on this chip. By taking advantage of LongRun2 technology, NEC was able to increase performance on their M2 chip while maintaining the same power characteristics as the previous generation. NEC utilized low threshold transistors to increase performance and implemented back bias to reduce worst case leakage to an acceptable level. Also see NEC’s press release at http://www.necel.com/news/en/archive/0707/0401.html.
Transmeta’s Efficeon microprocessor implemented LongRun2 to reduce worst case total power by 2.6 times without affecting speed.
LongRun2 technology has been licensed by Fujitsu, Intel, NEC, NVIDIA, Sony, and Toshiba.
LongRun2 IP
Transmeta has silicon-proven hard IP available to implement LongRun2 on SoC type designs. The IP consists of three blocks: Monitor Circuits, Controller and Bias Voltage Generator shown in Figure 3. The Monitor Circuits are ring oscillators whose frequency is dependent upon the circuit performance (speed), NMOS transistor leakage and PMOS transistor leakage. The Controller senses these frequencies and adjusts Vdd, P-Well Voltage (VPW), and N-Well Voltage (VNW) to minimize power while maintaining the performance required for desired operation.
Transmeta has experience integrating LongRun2 technology into designs for production. Integration Guide and Product Engineering Application Notes are available to assist in LongRun2’s design and productization. The Integration Guide provides an EDA flow and guidance on how to easily handle unaffected analog and IO circuits. The Product Engineering Application Note instructs how to calibrate the monitor circuits to the design’s performance and how to determine the programmed value of the fuses. In production, the fuses provide the target settings for the monitor circuits so that the controller can achieve minimum active power. Fuses, one-time-programmable (OTP) devices, are generally available off-the-shelf for most foundry processes. Figure 3 – LongRun2 IP
Dramatic Power Reduction
Transmeta’s LongRun2 technology provides a set of solutions to reduce variation across a distribution of parts which can improve the power specification, performance, yield, and reduce costs. Results will vary according to the design and how well the process works with LongRun2. The table below shows logic leakage reduction for a sample of process sizes.
The advantage of LongRun2 over other low power techniques is that it not only reduces power but also decreases the effects of process variations through post-process corrections. By reducing the effects of processes variability, the design specification can be tightened to achieve higher yield and lower power more effectively than with pre-process techniques. Other power reduction techniques are pre-process techniques only and do not address the process variation issue.
Before joining Transmeta, Mr. Hillman served as Vice President of Engineering for MOSAID Technology, a licensor of semiconductor intellectual property. Mr. Hillman joined MOSAID as a result of MOSAID's acquisition of Virtual Silicon Technology, a privately held supplier of semiconductor intellectual property, where Mr. Hillman served as vice president of engineering through its acquisition by MOSAID in 2005. Before joining Virtual Silicon, Mr. Hillman served as vice president of engineering for inSilicon, a provider of communications semiconductor intellectual property, which was acquired by Synopsys. Previously, he was also the Corporate Application Group director for the Physical Synthesis Business Unit of Synopsys for eight years. Mr. Hillman also spent 11 years at Apple Computer as a hardware manager where he was directly involved in the design of the Apple IIGS, Macintosh computer, and also led a team that developed the IEEE 1394 (Firewire) Serial Bus. He began his career at RCA Corporation and Zilog Corporation.
