Auto Industry Replaces Fuse Technology with Standard CMOS Based MTP; Adds Functionality, Testability and Reliability

By Craig Zajac
Virage Logic

The automotive industry has always set the bar in terms of quality and reliability metrics. Yield issues that cause a production line to go down can cost a manufacturer millions of dollars per day, and a field failure that requires a product recall can run into the hundreds of millions of dollars.

Non-volatile memory (NVM) has long been a critical part of automotive electronics. Traditionally, there have been two major NVM options available. One is embedded flash that is used in the ever increasing number of microcontrollers and ASICs for code storage and user data. The second is fuse technology that has been used for all the configuration, calibration, and trim settings for the various analog and sensor components.

Both technologies have advantages and disadvantages. Embedded flash offers high density and reprogrammability, but comes at the cost of a more complex manufacturing process. Fuse technology has been around for decades with a long history (both good and bad), but is limited to a single write cycle and often requires special high voltages during programming.

Recently the automotive industry has begun to move beyond traditional one time programmable (OTP) fuse technology and has started looking at multiple time programmable (MTP) NVM for calibration and trim settings. There are two main drivers for migrating away from OTP:

1. Increased sophistication of electronics requires more in-field calibration. Many of the latest precision components (sensors, analog) can benefit from in-field calibration to account for environmental variables and aging characteristics. Reprogramming in the field is impossible with fuse technology.
2. More stringent reliability targets mandate improved testability. Even trim settings or identification numbers that are programmed once are migrating to MTP. Automotive system manufacturers are requiring that all semiconductor components are 100% tested before shipped, and in some cases tested at multiple temperatures. OTP solutions are inherently untestable, and are a weak link in overall product quality. MTP solutions on the other hand, allow for several program and erase cycles during test to guarantee performance before the final value is programmed in-system.

With the cost of failure being so high, the automotive industry is moving forward very deliberately in their transition to more flexible NVM capabilities. Any new technology must be completely vetted and proven before it can be integrated into automotive electronics. Anticipating the migration to MTP solutions, Virage Logic has developed a full line of standard CMOS based embedded MTP optimized for the automotive market, and has recently completed full qualification on the world’s first automotive grade MTP in a standard CMOS process that meets automotive level quality and reliability requirements. Virage Logic builds in quality and reliability for each stage of the product development, from initial design all the way through silicon testing and production manufacturing.

At the most basic level, the reliability of the product starts before the physical design phase begins, when the product architecture is defined and evaluated and continues through the various design choices. The key to a robust and reliable design is to follow a rigorous methodology including the following:

• Design Failure Mode Effect Analysis (DFMEA) - the DFMEA process looks at all of the potential weaknesses and failure points in a given design and enables the development team to identify, document, and implement improvements to address the highest risk items. The DFMEA process and document is generated at the beginning of each design and leverages the latest best practices both from the industry and internal developments
• Architectural decisions - Virage Logic's AEON® family of embedded MTP includes a full differential bit cell providing 100% redundancy, fully integrated error correction, or both, for automotive grade products.
• Design margin - Virage Logic designs automotive level NVM products to meet full operation (both program and read) at 150°C that meets the automotive grade 0 requirements. Even for applications that do not require extreme operating temperatures such as remote keyless entry and infotainment, designing and qualifying to 150°C provides margin over the required operating range.

The silicon testing requirements for automotive grade products are above and beyond anything that is required for consumer and industrial applications. Virage Logic models the silicon testing after the AEC-Q100 standard. With product lifetimes exceeding 10 years, the non-volatile memory retention requirement is often set at 20 years at maximum temperature, and write cycle endurance requirements are typically 100k or greater. Demonstrating <10 ppm quality levels (ideally <1 ppm) for these specifications creates a significant challenge in testing.

Demonstrating 20-year retention would not be feasible without the use of temperature acceleration. Virage Logic does extensive testing to extract the activation energy of the intrinsic retention to calculate the required bake time and temperature. The results of the silicon testing are used to define the recommended production test flow, as well as the detailed pre-screen for the qualification testing.

Justifying manufacturability without manufacturing hundreds or thousands of wafers requires testing across process splits. All the standard split conditions are used (threshold voltage and poly CD), as well as a couple of non-volatile memory specific splits. Full parametric testing is done to establish both functionality and margin to specification. A portion of the process split material is also used in the full three lot qualification flow that was designed to meet the AEC-Q100 requirements. Endurance at multiple temperatures needs to be checked, and data retention at both high temperature and room temperature. The maximum temperature for data retention is determined by the maximum temperature limit of the IP. For a 150°C limit, the high temperature retention leg is performed at a temperature > 200°C. All data retention tests are run for over 2,000 hours. The final leg of the qualification is the dynamic high temp operating life test (DHTOL) that continuously stresses the NVM array at both elevated temperature and operating voltage.

The third component of building automotive level quality into standard CMOS NVM is the release to manufacturing. Because products will run for a number of years (up to 10 or 20), it is critical for 3^rd party IP vendors to provide the foundry with enough information and access to monitor the process over time. Virage Logic works closely with our foundry partners and provides a recommended scribe line structure that includes all custom high voltage devices, a bit cell, and devices that can be used to monitor the FN tunneling used for program and erase.

For the end user, the AEON family of non-volatile memory IP includes a wide array of test modes for production test, as well as failure analysis and debug. The test modes are designed to give users the ability to measure and / or override all of the key analog blocks within the IP.

There is a growing trend in the automotive industry to add functionality and improve the overall testability and reliability of the system by replacing traditional fuse technology with standard CMOS based MTP. The key to developing standard CMOS MTP for the automotive industry is in the procedures and methodology used throughout development. Virage Logic's AEON product is the world's first multiple time programmable NVM that has been qualified to automotive criteria on a standard CMOS process.

Explore IP from Virage Logic here.

Explore complete IP catalog from Virage Logic here.

About the Author

Craig Zajac is the Senior Product Marketing Manager for the NVM business unit at Virage Logic. He is responsible for Virage Logic's comprehensive line of standard CMOS NVM products including both the AEON and NOVeA® product lines. He previously worked in the IP division of Impinj and has extensive experience in the semiconductor industry including stops at National Semiconductor, ON Semiconductor, and Motorola.