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Find the latest trends and technical details on semiconductor IP from the industry's leading IP vendors

  • Wearables and IoT Devices Demand Lowest-Leakage, Lowest-Voltage SRAMs
  • Tuesday September 16, 2014 — Mobile Semiconductor
  • With increased consumer demand for wearable devices and the emerging market for the Internet of Things (IoT), the demand for extremely low-voltage, low-leakage memory that can provide high performance is growing. Off-the-shelf memories cannot meet both the low power and high performance requirements of wearable designs. SRAM compilers designed to operate at the lowest voltages must be used to achieve necessary reliability with high yields of memory instances.

  • Low-Power Processor Solutions for Always-On Devices
  • Tuesday September 09, 2014 — Synopsys
  • Increasingly, mobile devices are becoming context-aware, using a broad array of sensors to monitor location, movement, heart rate, sound, etc. These sensor inputs enable new applications that make our smart mobile devices even smarter and are changing the way users interact with the devices. Think, for example, of devices with an "always-listening" capability that can be activated by means of a voice command.

  • Meeting NVM Requirements for Evolving Mobile Computing Platforms
  • Tuesday September 02, 2014 — Sidense
  • Mobile computing is one of the most rapidly expanding market segments in the electronics industry. Many within the industry have chosen to include mobile communications within the mobile computing segment since so many mobile computing devices, such as smartphones and newer tablets, include communications capabilities. Shrinking PC purchases are being offset by mobile computing and communications device sales, with compute mobility becoming a "most have" for many consumers. According to IDC shipments of smartphones will be 1.2B units in 2014 while Statista predicts that tablet shipments will top 260M units this year.

  • Reducing Power Consumption while increasing SoC Performance
  • Tuesday August 19, 2014 — ChipStart
  • Designers of today's high-performance multi-client SoCs struggle to achieve the best possible performance/watt for their designs. Every generation of product must improve the customer's user experience by delivering more performance. While at the same time battery life must increase with each subsequent product generation. Performance-IP has developed a family of products based on its patent-pending Memory Tracker TechnologyTM. This technology enables products to operate at higher levels of efficiency, reducing power consumption while increasing SoC performance.

  • Quantifying Entitlement for 14/16nm Technologies
  • Tuesday August 12, 2014 — eSilicon
  • Consider the decrease in the number of tapeouts and the number of design teams as well as the loss of critical industry expertise in advanced technology nodes. Couple this with the increase in the tools required per tapeout, the design risk and the cost per tapeout, and we see a new type of bathtub curve emerging. This curve sets the stage for understanding why there is an uptick in the price per gate at 20nm and below.

  • 3D Memory Landscape Takes Shape
  • Tuesday August 05, 2014 — Cadence
  • 3D technology is reshaping the memory landscape for virtually all types of electronic products. The driving force behind 3D is the fact that while processor performance has continued to increase in accordance with Moore's Law, memory performance has not. In fact, memory performance has been a fundamental limiting factor in electronic equipment from its earliest days. The very reason we have tiered memory architectures (L1 cache, L2, L3, main memory) is a tacit acknowledgment of this. The performance limit imposed by memory is well known and is commonly referred to as the "memory wall". While the memory wall has seemed insurmountable for a number of years, new 3D memory technologies are now poised to tear down that wall. This article reviews the major 3D memory approaches and introduces verification IP (VIP) products that facilitate their implementation.

  • Delivering on the Promise of Guaranteed Isochronous Traffic in USB 3.1
  • Tuesday July 29, 2014 — Synopsys
  • Over the years, certain communication protocols have included a special class of traffic, called isochronous, that provides Quality of Service (QoS). Unlike file transfers in computer systems, isochronous data transfers do not need guaranteed delivery, but they do need guaranteed service opportunities. Typical examples of isochronous traffic are audio and video streams where the synchronization of the two must be strictly maintained and the latency must be kept to a minimum, but a slight glitch in either one does not result in devastating data corruption.

  • Building a Better Packet Buffer
  • Tuesday July 22, 2014 — Memoir Systems
  • A vast network of networks, the Internet essentially does one task remarkably well; it quickly and reliably moves digital information in the form of data packets between data centers and billions of end users. Propelling these packets is a huge constellation of routers and switches that behind the scene directs and forwards network traffic. The pace of the network is affected by a number of factors, not the least of which is the packet buffer, a memory-based data structure at the heart of the network chips that operate within every switch and router. As a packet arrives at a switch, for example, its contents must be stored in memory long enough for the switch to determine what to do with it and where to send it. During that window of time, if another packet arrives, it too must be stored in memory until the switch can process it, and so on with the next packet. Packet buffers reduce packet loss by absorbing transient bursts of traffic when routers or switches cannot immediately forward them. They are also instrumental in keeping output links fully utilized during congestion.

  • Choosing IP for Low Video Latency
  • Tuesday July 08, 2014 — CAST
  • Video latency is the amount of time between frame capture and display. Low latency makes interacting with video effective and satisfying. Latency under 100ms is low enough for conferencing because humans don't perceive a delay that small. But in industrial or medical systems where a machine interacts with video, latency requirements can be much lower: 30ms, 10ms, or less.

  • A guide to the new PowerVR Rogue GPUs
  • Tuesday July 01, 2014 — Imagination Technologies
  • 2014 marks the expansion of the PowerVR Rogue architecture with two new families of GPUs designed to enrich what is already the best roadmap for graphics the mobile and embedded industry has seen. The new PowerVR Series6XT and Series6XE Rogue architectures drive performance to new levels while reducing power consumption even further.

  • Setup/hold interdependence in the pulsed latch (Spinner cell)
  • Tuesday June 24, 2014 — Dolphin Integration
  • The frequency of the very large Systems-on-Chip continuously increases over the years. Operating frequencies of up to 1 GHz are common in modern deep sub-micrometer application specific integrated circuits. The verification of timing in VLSI circuits is achieved by means of static timing analysis (STA) tools which rely on data described in the cell libraries to analyze the circuit. The characterization of the individual cells in cell libraries is therefore highly critical in terms of accuracy of the STA results. Inaccurate characterization of constraint timings causes the STA results to be either overly optimistic or pessimistic. Both cases should be avoided as the optimistic case can cause a fabricated circuit to fail, whereas the pessimistic case unnecessarily degrades circuit performances.

  • Secure Memory for an Increasingly Connected World
  • Tuesday June 17, 2014 — Sidense
  • With the proliferation of the Internet of Things (IoT) ecosystem and all of its interconnected components, security of both data and intellectual software property has gotten a lot of attention, and rightfully so. Much of this attention, however, has focused on securing "data in transit" - data flowing between devices, usually in a wireless mode. However, we need to also be very concerned with the security of information stored in memory at the many separate nodes within an interconnected network, whether that network is part of an automobile, a smart home, the national power grid or some other IoT-like system. Protecting this "data at rest" is where the physical security of the memory being used to stored data or code needs to be carefully considered.

  • Optimized Memory for Hardening CPU, GPU and DSP Cores
  • Tuesday June 10, 2014 — Synopsys
  • System-on-chips (SoCs) targeted at the mobile phone, tablet and Smart TV segments use many different kinds of cores - CPUs, GPUs and DSPs. Each of them have different performance, power and area (PPA) requirements. The CPUs need high speed while the GPUs seek to drive down area and power. Base-station applications require high speed DSP implementations while most others only require speeds under 400 MHz. This article presents memory design techniques that enable SoC designers to concurrently meet all of these seemingly conflicting goals.

  • Why IP is the Next Learning Curve in Semiconductor
  • Tuesday June 03, 2014 — IPextreme
  • I attended a fascinating keynote presentation by Wally Rhines of Mentor Graphics on April 17th at the Electronic Design and Processes Symposium in Monterey. As is his custom, Wally shared with the dinner crowd a dazzling set of data around the reasons why semiconductor is no longer driven by Moore's Law, but rather by semiconductor learning curves. Such learning curves are typical in mature industries.

  • Understanding Interrupt Latency in Modern 8051s
  • Tuesday May 27, 2014 — CAST
  • Systems in today's fast-growth application areas--Internet of Things, smart automobile systems, wearable electronics, etc.--require a large number and variety of focused, inexpensive, low-energy subsystems. This sets the stage for a new microcontroller war between 32-bit processors--who thought they had already won--and 8-bit veterans like the 8051--who have undergone a fitness regimen and returned to the field with new vigor.

  • Why Verification IP Matters
  • Tuesday May 20, 2014 — Cadence
  • What is verification IP (VIP), and why does it matter? To understand VIP, let's compare it with something well understood by most readers of this column - design IP. System-on-chip (SoC) designs are understood to be vastly complex machines that are assembled out of subsystems containing multiple design IP components. Because of the pervasive use of standard interfaces such as DDR, Ethernet, PCI Express, USB, and a host of others, it is relatively easy to integrate design IP from multiple sources. Better yet, the broad availability of commercial design IP means that components can be purchased for a wide array of applications, offloading the design task from SoC developers.

  • Understanding the MIPI M-PHY
  • Tuesday May 13, 2014 — Synopsys
  • Consumers today demand higher performance, feature-rich applications, and higher quality multimedia content in their mobile devices. To design these high-performance devices, designers need to contend with pin count and channel limitations (including the physical dimensions, cost, and package reliability) as well as bandwidth bottlenecks. At the same time, battery operated mobile devices strive for very low power consumption in active and idle periods with quick entry and exit times.

  • MIPS Series5 Warrior CPUs: the next revolution in processor IP from Imagination
  • Tuesday May 06, 2014 — Imagination Technologies
  • Building on the success of the award-winning Aptiv generation of CPU cores, Imagination is now busy designing the next generation of MIPS processors. Codenamed Warrior, the MIPS Series5 CPUs feature cores based on the MIPS32 and MIPS64 instruction set architectures, with a focus on superior performance efficiency across the high-end, mid-range and entry-level/microcontroller CPUs.

  • Full hardware processing of NVMe commands
  • Tuesday April 22, 2014 — IP-Maker
  • The NVM Express (NVMe) specification defines a command set for PCIe-based Solid-State Drives (PCIe SSDs). It is a host/device architecture, where the hosts are the CPU cores of a server, and the device is a PCIe SSD. A standard NVMe driver is available on the host side for different operating system platforms (Linux, Windows...). On the device side, the NVMe specification must be implemented in a SSD controller, where it could be a hardware or a software architecture. This paper describes a hardware implementation of the command management and its numerous benefits.

  • PCI Express Gen 4 - a Big Pipe for Big Data
  • Tuesday April 15, 2014 — Cadence
  • Big Data is more than a buzzword. It's a reality today in several applications and will increasingly become a constant companion for each of us, just as our smartphones are today. But Big Data requires a big pipe to deliver it, and that pipe may soon be bottlenecked. At the heart of every server today are constricted arteries - PCI Express lanes that don't have the capacity for Big Data applications. Now, however, a new interface specification, PCI Express Gen 4, is being rolled out to dramatically boost server throughput. That interface comes at a critical time for server development, and its rapid adoption is key to the continued success of the electronics industry. But PCI Express Gen 4 also poses a number of challenges for design and verification teams - challenges they need to consider today.

  • Optimizing Power, Performance and Area (PPA) of your Embedded System with Configurable Processor Extensions
  • Tuesday April 08, 2014 — Synopsys
  • Embedded processors are ubiquitous in the products we use on a daily basis, from devices requiring high-performance like smart phones and tablets, to devices with low energy consumption requirements, including medical monitors, hearing aids and wearable electronics. These electronic devices are increasingly required to execute a greater number of functions while consuming less power and silicon area. While newer process technologies address these low power/high performance requirements to some extent, they cannot keep up with the performance, power and area requirements of advanced battery-operated devices. Additional techniques are needed in order to deliver more features with higher performance, lower area and less power consumption. This article explores how Synopsys' DesignWare® ARC® Processors and ARC Processor EXtensions (APEX) technology can optimize processor power and performance.

  • Choosing the Best High-Speed ADC for Your SoC
  • Tuesday April 01, 2014 — S3 Group
  • Consumer's voracious appetite for quick access mobile content is obligating the need for high-resolution, high-speed data converters in their mobile internet devices. Whether the transmission pipe is via cellular networks such as LTE or via local networks such as WiFi, the end requirement for the data converter remains largely the same, those being higher bandwidth, higher speed, lower power and ownership costs that the consumer market can tolerate.

  • Understanding Interrupt Latency in Modern 8051s
  • Tuesday March 25, 2014 — CAST
  • Systems in today's fast-growth application areas--Internet of Things, smart automobile systems, wearable electronics, etc.--require a large number and variety of focused, inexpensive, low-energy subsystems. This sets the stage for a new microcontroller war between 32-bit processors--who thought they had already won--and 8-bit veterans like the 8051--who have undergone a fitness regimen and returned to the field with new vigor.

  • How to make THE difference in power management architecture
  • Tuesday March 18, 2014 — Dolphin Integration
  • To reduce the Bill-of-Material (BoM) and to simplify their usage, System-on-Chips (SoC) become more and more complex due to the integration of a large number of features previously located on board. This increase of complexity, combined with economic and green stakes leads to draw new optimizations, such as partitioning the SoC in different subsets with power and voltage islets supporting several states of activity. Theses states allow minimizing power consumption for islets that are not used or are operating with reduced speed performances.

  • Reduce Test Cost and Shorten Design Cycle with Hierarchical SoC Testing
  • Tuesday March 11, 2014 — Synopsys
  • SoC test has become very complex. The combination of increasing design sizes, the growing use of IP and greater design complexity has made SoC testing a challenge. As designs become larger, the traditional full chip test methodologies are proving increasingly challenging due to power consumption and long test development times that make testing of large SoCs inefficient. Designers need a test solution that can effectively test their large designs, which contain a variety of IP and design blocks, while maintaining low test cost and high productivity.

  • Data at the center of RF Foundry Growth
  • Tuesday March 04, 2014 — GLOBALFOUNDRIES
  • No one could have imagined the impact of the mobile handset on society when it was first introduced commercially over 20 years ago. Today we depend on our cell phones for many different tasks from making simple calls to watching high definition live video. Not only has this device changed the way we work and play, but it has also transformed the network and created a vehicle for operators to monetize their investment. There is no doubt that the consumption of data is at the center of mobile handset growth and there are three major industry trends that will continue to not only drive demand for handsets but create industries and applications which will leverage the wireless network. All of these trends contribute to the growth in RF foundry.

  • Choosing the Best High-Speed ADC for Your SoC
  • Tuesday February 25, 2014 — S3 Group
  • Consumer's voracious appetite for quick access mobile content is obligating the need for high-resolution, high-speed data converters in their mobile internet devices. Whether the transmission pipe is via cellular networks such as LTE or via local networks such as WiFi, the end requirement for the data converter remains largely the same, those being higher bandwidth, higher speed, lower power and ownership costs that the consumer market can tolerate.

  • Uncovering MIPI UniPro - a Key Interface for Future Mobile Devices
  • Tuesday February 18, 2014 — Cadence
  • With 1.9 billion mobile phones expected to be shipped in 2014 and 54% growth anticipated in ultramobile (tablet, hybrid, and clamshell) shipments, mobile device developers are eager for a standard design infrastructure and practice to streamline the development of new products. Leveraging standard communication interfaces allows developers to focus on creating unique added value in their designs - differentiation that is crucial for survival in this ultra-competitive market.

  • Game-Changing DDR Memory IP
  • Tuesday February 11, 2014 — Uniquify
  • Most owners of consumer electronics have no concept of the role IP plays in the design of their HDTVs, MP3 players, video recorders, cell phones and so forth. And, why should they? The device works just fine -- no need to look under the hood.

  • Fast Development of ISP Algorithms with MIPI IP and FPGA Platform
  • Tuesday February 04, 2014 — Cadence
  • From smart TVs with gesture control to the high-resolution cameras integrated into today's smartphones to applications boasting multiple cameras, image processing has become a key component in many consumer electronics products. To support the need for more pixels and fast-changing requirements, designers are finding that they must offload some image processing from the application processors. That's why image system processing (ISP) is integral to the design of today's systems on chip (SoCs).

  • Using Cost-Effective and Secure Field-Programmable 1T-OTP to Emulate MTP
  • Tuesday January 28, 2014 — Sidense
  • Applications for non-volatile memory (NVM) encompass a wide range of programming requirements. Some products require one-time programmable (OTP) memory that is programmed during chip fabrication – mask ROM is good for this purpose if the code is frozen. Other products need field-programmable OTP for applications such as analog trimming, necessitating the use of secure in-system programmable NVM.

  • Xilinx Plug-and-Play IP: Accelerating Productivity and Design Reuse
  • Tuesday January 21, 2014 — Xilinx
  • As today's designs integrate increasing amounts of functionality, designers must have access to proven, up-to-date, easy-to-use IP from reliable sources to accelerate their design cycles. The ability to deliver high-performance systems at the lowest total design cost on time and within budget depends upon the ability to rapidly combine and configure dozens or hundreds of design elements including on-chip logic blocks, processor cores, and a wide range of IP cores. The Plug-and-Play IP initiative is the Xilinx response to the growing customer demand for system-level design support for the use of multiple IP cores from diverse internal and third-party sources. Plug-and-Play IP cores from Xilinx and its Alliance Program members meet this demand by providing simple yet powerful capabilities that vastly improve designer productivity by supporting easier IP reuse, allowing design teams to create complex systems with minimal effort.

  • Why do you need a hardware solution to secure your embedded system?
  • Tuesday January 14, 2014 — Barco Silex
  • Every day, smartphones, servers, computers and other devices are exchanging enormous amounts of data. And the number of connected devices will grow significantly in the next decade. As will the many applications and services across a wide variety of markets that will require security - from payment, broadcast, audio, navigation, pay-tv, networking and wireless systems to automotive, healthcare, defense and space applications. Each one has their own specific performance constraints and security levels, to meet the level of perceived threat of attack.

  • Overcoming Security Protocol Bottlenecks at 10 Gbps, 40 Gbps and Beyond
  • Tuesday January 07, 2014 — INSIDE Secure Corporation
  • Geometric growth in worldwide Internet traffic is driving demand for corresponding increases in networking bandwidths. According to the Cisco Visual Networking Index, worldwide IP traffic will grow at a compound annual growth rate (CAGR) of 23 percent from 2012 to 2017, with 'busy hour' traffic growing even faster. Network infrastructures must deliver throughput that keeps pace.

Blogs

  • CDN LIVE Conference
  • Moore's Cycle, Fifth Horseman, Mixed Signals, and IP Stress
  • IP Insider Blog-By John Blyler
    Posted 3.23.2013
  • What do all of these things have in common? They were key topics addressed by Cadence...