Find the latest trends and technical details on semiconductor IP from the industry's leading IP vendors
To reduce the Bill-of-Material (BoM) and to simplify their usage, System-on-Chips (SoC) become more and more complex due to the integration of a large number of features previously located on board. This increase of complexity, combined with economic and green stakes leads to draw new optimizations, such as partitioning the SoC in different subsets with power and voltage islets supporting several states of activity. Theses states allow minimizing power consumption for islets that are not used or are operating with reduced speed performances.
SoC test has become very complex. The combination of increasing design sizes, the growing use of IP and greater design complexity has made SoC testing a challenge. As designs become larger, the traditional full chip test methodologies are proving increasingly challenging due to power consumption and long test development times that make testing of large SoCs inefficient. Designers need a test solution that can effectively test their large designs, which contain a variety of IP and design blocks, while maintaining low test cost and high productivity.
No one could have imagined the impact of the mobile handset on society when it was first introduced commercially over 20 years ago. Today we depend on our cell phones for many different tasks from making simple calls to watching high definition live video. Not only has this device changed the way we work and play, but it has also transformed the network and created a vehicle for operators to monetize their investment. There is no doubt that the consumption of data is at the center of mobile handset growth and there are three major industry trends that will continue to not only drive demand for handsets but create industries and applications which will leverage the wireless network. All of these trends contribute to the growth in RF foundry.
Consumer's voracious appetite for quick access mobile content is obligating the need for high-resolution, high-speed data converters in their mobile internet devices. Whether the transmission pipe is via cellular networks such as LTE or via local networks such as WiFi, the end requirement for the data converter remains largely the same, those being higher bandwidth, higher speed, lower power and ownership costs that the consumer market can tolerate.
With 1.9 billion mobile phones expected to be shipped in 2014 and 54% growth anticipated in ultramobile (tablet, hybrid, and clamshell) shipments, mobile device developers are eager for a standard design infrastructure and practice to streamline the development of new products. Leveraging standard communication interfaces allows developers to focus on creating unique added value in their designs - differentiation that is crucial for survival in this ultra-competitive market.
Most owners of consumer electronics have no concept of the role IP plays in the design of their HDTVs, MP3 players, video recorders, cell phones and so forth. And, why should they? The device works just fine -- no need to look under the hood.
From smart TVs with gesture control to the high-resolution cameras integrated into today's smartphones to applications boasting multiple cameras, image processing has become a key component in many consumer electronics products. To support the need for more pixels and fast-changing requirements, designers are finding that they must offload some image processing from the application processors. That's why image system processing (ISP) is integral to the design of today's systems on chip (SoCs).
Applications for non-volatile memory (NVM) encompass a wide range of programming requirements. Some products require one-time programmable (OTP) memory that is programmed during chip fabrication – mask ROM is good for this purpose if the code is frozen. Other products need field-programmable OTP for applications such as analog trimming, necessitating the use of secure in-system programmable NVM.
As today's designs integrate increasing amounts of functionality, designers must have access to proven, up-to-date, easy-to-use IP from reliable sources to accelerate their design cycles. The ability to deliver high-performance systems at the lowest total design cost on time and within budget depends upon the ability to rapidly combine and configure dozens or hundreds of design elements including on-chip logic blocks, processor cores, and a wide range of IP cores. The Plug-and-Play IP initiative is the Xilinx response to the growing customer demand for system-level design support for the use of multiple IP cores from diverse internal and third-party sources. Plug-and-Play IP cores from Xilinx and its Alliance Program members meet this demand by providing simple yet powerful capabilities that vastly improve designer productivity by supporting easier IP reuse, allowing design teams to create complex systems with minimal effort.
Every day, smartphones, servers, computers and other devices are exchanging enormous amounts of data. And the number of connected devices will grow significantly in the next decade. As will the many applications and services across a wide variety of markets that will require security - from payment, broadcast, audio, navigation, pay-tv, networking and wireless systems to automotive, healthcare, defense and space applications. Each one has their own specific performance constraints and security levels, to meet the level of perceived threat of attack.
Geometric growth in worldwide Internet traffic is driving demand for corresponding increases in networking bandwidths. According to the Cisco Visual Networking Index, worldwide IP traffic will grow at a compound annual growth rate (CAGR) of 23 percent from 2012 to 2017, with 'busy hour' traffic growing even faster. Network infrastructures must deliver throughput that keeps pace.
What do all of these things have in common? They were key topics addressed by Cadence...