In the News

EVE to Exhibit at IIC-China in Shenzhen, China
02/22/2012

Altera Demonstrates First FPGAs to Interoperate with 100-Gbps Optical Module
02/21/2012

Synopsys Announces DesignWare Embedded Memories and Logic Libraries for TSMC 28-nanometer Processes
02/14/2012

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Tech Talks

IP Support to Enable ONFI 3 Advantages
Cadence (01/24/2012)

When Once Is Not Enough
Technology Choices for Few- and Multiple-Time Programmable Non-Volatile Memory
Synopsys (01/10/2012)

DDR4: Double the speed, double the latency?
Make sure your system can handle next-generation DRAM
Cadence (11/22/2011)

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White papers

Unleash the Performance Benefits of Sigma-Delta ADCs into Your SoC
Synopsys (01/27/2012)

Protect Your Electronic Wallet Against Hackers
Synopsys (11/21/2011)

Shrinking SoC Design Cycles Using DesignWare Intellectual Property
Synopsys (11/18/2011)

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VIP is prefabricated building blocks that you can drop into your flow to perform a predefined function. But instead of becoming blocks of the design itself, Verification IP blocks become parts of the testbench used in verification. Like other IP, verification IP can, in theory, be designed for reuse or licensed from third parties.