The exploding bandwidth demand from the cloud, artificial intelligence, machine learning (AI/ML), and 5G applications has driven the growing demand for high-speed connectivity and accelerated 112G SerDes market adoption. Cadence is the market leader in developing 112G PAM4 technology. The 112G Extended Long-Reach (ELR) SerDes PHY IP is the latest generation of the product family. It supports PAM4 and NRZ signaling and data rates from 1G to 112G. Incorporating industry-leading analog-to-digital converter (ADC) and digital signal process (DSP) technology, the IP provides a superior performance margin over high-loss and reflective channels, improves system robustness, and lowers the risks to production. It is also power and area efficient, allowing for high port-density application. Industry-leading customers have adopted the Cadence® 112G-ELR SerDes IP, and it is available in 4nm, 5nm, 6nm, and 7nm process nodes.
Market Trends of 112G SerDes
First, let us review the marketing trends of the 112G SerDes. Networking is the key market driver here. The 112Gbps lane rate has been adopted in 100G/200G/400G Ethernet and leads to 800G Ethernet using 8 lanes of 112G SerDes, as defined by the IEEE802.3df standard. With the growth in hyperscale data centers, the switch silicon bandwidth doubles every two years. 25.6TB switch products are available in the market, and next-generation 51.2TB is around the corner. These high bandwidth switches use 112G SerDes as the foundation IP with either 256 or 512 lanes of 112G in the SoCs. In addition to networking, the AI/ML workload with chip-to-chip interconnect between multiple training SoCs demands higher bandwidth using 112G SerDes in advanced process nodes. 5G applications are another strong driver. 56G SerDes has been used for 5G CPRI/eCPRI interfaces and next-generation 5G applications need 112G SerDes to provide higher bandwidth and lower latency.
Figure 1: Market Trends of 112G SerDes
112G SerDes Application Spaces
As Figure 2 shows, 112G PAM4 SerDes interfaces in a typical system are needed for Long Reach (LR), Medium Reach (MR), and Very Short Reach (VSR). The LR channel runs between the ASIC/FPGAs on two PCBs over a backplane or a copper cable with two connectors. This is typically used by networking applications. The MR interface provides chip-to-chip (C2C) interconnection within one PCB or two PCBs over a midplane with one connector. This is predominantly used by AI applications to connect multiple training SoCs. The VSR interface is also called the chip-to-module (C2M) interface. This uses an optical module as the front-end media. The channel consists of the PCB trace between the ASIC and the optical module with one connector.
Cadence is the market leader in developing 112G PAM4 technology. Cadence’s 112G PAM4 SerDes IP can support LR, MR, and VSR applications. We also provide power and area-optimized solutions for specific applications.
Figure 2: 112G SerDes Application Spaces
Benefits of 112G-ELR SerDes to Production Systems
112G PAM4 is made possible with sophisticated DSP processing to comply with standards-based connectivity. However, for challenging applications such as LR production systems, it is important to have an additional performance margin in SerDes than just the standard LR.
Additional margin in SerDes means achieving a lower pre-FEC bit error rate (BER) on a given channel, which allows the SoC designers to leverage a lighter FEC that has lower latency, lower power, and less area. Additional margin in SerDes also means higher tolerance in system impairments such as supply noise, reflections, and crosstalk, which translates to a robust design, more flexibility, and faster time-to-market. The diagram below shows reflection issues that might occur from the package, PCB, connectors, and other issues and greatly impact the link performance.
Figure 3: 112G System Impairments and Deployment Challenges
To compensate for the above-said system impairments and challenges, which are often inevitable, Cadence provides the 112G-ELR PAM4 SerDes IP that extends the reach capability and delivers greater margin, better flexibility, and lower risk of production.
Cadence 112G-ELR State-of-the-art DSP Techniques
To provide unprecedented performance, Cadence 112G-ELR PAM4 SerDes incorporates state-of-the-art DSP technologies such as reflection cancellation and maximum likelihood sequence detection (MLSD).
The reflection cancellation technique incorporates floating FFE taps to cancel spurious, far-out reflections in a product environment with practical traces and connectors. This provides robustness in BER outcomes on high-loss and reflective channels.
MLSD is especially useful for high insertion loss channels and provides improved burst-error handling capability. Via proprietary implementation techniques, Cadence ensures that the power overhead of MLSD is minimal. As Figure 4 shows, the MLSD engine is placed after the receiver's main equalization engine (FFE/DFE) and uses the Viterbi algorithm. Optionally, the MLSD output can be selected or bypassed depending on the specific channel conditions. Figure 5 describes the operating principle of the MLSD. Initially, no hard decisions are made on the post-equalized signal. All four possible errors are computed at any time (four targets for PAM4) and thus a trellis is constructed to explore all possible bit sequences across a fixed window of equalized samples. Then the maximum likelihood sequence is determined by minimizing the total error across the observable window of the trellis. MLSD can provide one order of magnitude BER improvement for high insertion loss scenarios.
Figure 4: 112G System Impairments and Deployment Challenges
Figure 5: MLSD Operating Principle
Figure 6: Cadence 112G-ELR SerDes Advantages
Cadence 112G-ELR SerDes has many advantages that provide our customers the best value of using the IP in their SoCs. The production quality of the IP is very important for our customers to lower the risk to production. The DSP-based architecture is a very mature solution that is silicon-proven in multi-generation Cadence test chips and customer products. The performance complies with and exceeds IEEE and OIF standard specifications. The start-of-the-art DSP techniques, including reflection cancellation and MLSD, effectively boost the performance margin, improve system robustness, and hence, reduce production risk and accelerate time to market. The optimized power and area are ideal for high port-density applications. To achieve fully autonomous startup and adaptation, the IP also has built-in intelligence including firmware-based adaptation, smart power optimizer, and on-die temperature sensor.
Cadence 112G-ELR SerDes Performance
Cadence 112G-ELR PAM4 SerDes IP is available in 4nm, 5nm, 6nm, and 7nm process nodes. The image below shows the 106.25Gbps transmitter eye diagram of the 112G-ELR IP in 5nm. You can clearly see the three eyes separating the four signal levels in PAM4 mode.
Figure 7: Transmitter Eye Diagram at 106.25Gbps, Cadence 112G-ELR IP in 5nm
Figure 8 shows the statistics of the digitally equalized signal at 106.25Gbps before the slicer as tallied by the on-die histogram engine within the RX DSP. This data indicates great BER performance.
Figure 8: Histogram of Pre-slicer Equalizer Output at 106.25Gbps, Cadence 112G-ELR IP in 5nm
Cadence High-Speed Ethernet Subsystem Solution
The 112G-ELR SerDes IP can be used with the Cadence High-Speed Ethernet Controller IP family to provide complete Ethernet subsystem solutions up to 800G. Cadence can provide full subsystem deliveries with integrated PHY and controller, enabling customers to ease integration and streamline their SoC designs. The High-Speed Ethernet Controller IPs comply with IEEE 802.3 and Ethernet Technology Consortium specifications. They can support single- and multi-Ethernet channel solutions. The IPs provide full-featured media access control (MAC), physical coding sublayer (PCS), forward error correction (FEC), and physical medium attachment (PMA) blocks for a complete architecture. For more information on Cadence’s High-Speed Ethernet Controller IPs, please visit Cadence High Speed Ethernet Controller.
The global data traffic will continue the trend of tremendous growth fueled by high-performance computing (HPC), AI/ML and 5G (and soon, 6G) communications, etc. Therefore, there is a constant need for higher signaling bandwidth and faster SerDes. The 112G SerDes market adoption will continue to grow for the next few years, while the ASIC designs with 224G SerDes will start soon.
Cadence is leading the way in providing high-speed 112G/56G SerDes, and soon the 224G SerDes IP solutions to the market. We continue to invest in design and interface IPs that address our customers’ rapidly evolving requirements. Our high-speed Ethernet subsystems with best-in-class PHY and feature-rich controller IP enable 100G/200G/400G/800G and soon 1.6T Ethernet solutions.
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