Semiconductor IP News and Trends Blog
5G connectivity Advanced with IP Building Blocks
Critical low power, high performance 5G connectivity gets closer with Imec’s latest semiconductor IP building ADC and RF front-end SOC building blocks.
By John Blyler, Editor, JB Systems Tech
An important element for future Internet-of-Things (IOT) connectivity will be emerging 5G connectivity technologies. Imec, an international nanotechnology R&D institution, recently announced two key building blocks for low-power 5G applications: a SAR-based analog-digital-converter (ADC) and a 60GHz radio front-end subsystem. These technologies are offered as intellectual property (IP) blocks for system-on-chip (SOC) designers. To learn more about these IP blocks and their importance to 5G, I asked a number for questions of Joris Van Driessche, program manager of perceptive systems at imec. What follows is a portion of that discussion. — JB
Blyler: What 5G requirements make these two IP blocks so important?
Van Driessche: 5G mobile networks promise massive connectivity through much higher data rates, lower latency and lower battery consumption than current 4G standards. This is achieved at frequencies below 6GHz and also millimeter-wave implementations that provide low-latency speeds of multi-Gigbit per sec (Gb/s).
Achieving this promise requires an energy efficient, low-cost, compact 60GHz front-end IC that supports a variety of antennas. Supporting various antennas are required for fixed wireless access and small cell backhaul. A modular architecture for the IP helps to support of customers equipment (16-32 antennas) as well as basestations (up to 256 antennas)
In addition to the above, 5G systems must be very low-power. Imec has developed a compact, low power, low cost yet high-speed (300M/s) analog-digital-converter (ADC) that meets the requirements of multimode multiband 5G communications (see Figure 1). Further, the low dynamic power consumption of 3.6mW at 300MS/s is ideal to support the many different signal bandwidths below 6GHz. This is critical as power consumption scales linearly with sampling frequency.
Blyler: In what way are these IP blocks “novel,” as noted in the press release?
Van Driessche: The 60GHz front-end IP module has on-chip transmit-receive switching, which enables the sharing of the antenna array between transmit (TX) and receive (RX) modes (see Figure 2). Typically, the loss and the limited linearity of such an on-chip transmit-receive switch constrains the TX output power while increases the RX noise figure. With our IP, a novel topology has been implemented that has very little impact on the transmitter output power and the receiver sensitivity.
As for the ADC, capacitive successive-approximation-register (SAR) architectures are among the smallest form factor and most energy efficient for medium resolutions and speeds, ideal for multi-mode multi-band solutions. However, such SAR ADC architecture poses tough constraints on the reference voltages to avoid harmonic distortion at the ADC output. Traditional solutions either include high-speed reference buffers or, alternatively, large decoupling capacitors but at the expense of significant power consumption or area. In our IP block, a novel calibration technique is used that stabilizes the reference with only a small power and area cost.
Blyler: Why are “8-way calibration-free beamforming at RF frequencies” important in 5G systems?
Van Driessche: At millimeter wave frequencies beamforming is essential to overcome the high propagation loss which is typical at these frequencies. To provide data rates of multi-gigabit per second and also coverage over several hundreds of meters, this demands large scale antenna arrays (up to 256 antennas for basestations) to improve the link budget.
To limit complexity of these large antenna array chips or modules, RF beamforming seems the only viable approach as it maximally avoids duplication of more IP building blocks. Previously published CMOS RF beamformers suffer from a dependence of gain (or loss) on the phase shift, requiring a complex calibration procedure. In our 60GHz front-end module IP, which can be used as a modular building block for larger antenna arrays, the gain values are flat over the phase shift values and as a result it does not require any calibration. This gives an advantage in terms of cost.
Blyler: The press release notes that the IP uses “scaled CMOS technologies.” Are RF SOI and SiGe technologies also supported? Why or why not?
Van Driessche: We have a strong IP track record that leverages on scaled CMOS (28nm and beyond). However, we also have experience with other technologies (SiGe, RFSOI, FDSOI, and others.) Really, the optimum process technology depends on the application and the targeted specifications, which we help our customers determine from IP block selection through process node and packaging technologies. (See, “The Technical and Business Side of Custom SoCs“)
Blyler: What is the general status of 5G? Has the standard been approved yet?
Van Driessche: There is no short answer to this question because standardization is a complex process with many parallel activities and a pipeline of stages and development phases.
The 5G standard is being defined within 3GPP. Phase 1 of 5G is being defined in Release 15 that started during 2016 and is scheduled to end in 2018. There are several stages covering service description, architecture definition and definition of the implementation and physical layer. 5G phase 1 is dubbed “New Radio” (NR), a networking fabric that will connect smartphone, cars, utility meters, and more things in the IOT.
Phase 2 of 5G will be defined in Release 16, the standardization of which will probably last until end of 2019.
These standardization of 5G Phase 1 (release 15) and 5G Phase 2 (release 16) should lead to large-scale deployments in 2020 and 2021 respectively. Small scale deployments could happen earlier.
Blyler: Thank you.