Semiconductor IP News and Trends Blog
A Brief Introduction to Analog Integration in ASICs and SoCs
Application-Specific Integrated Circuits (ASICs) are systems that are designed for specific applications and can be fully customized and optimized for specific tasks. Contrary to general-purpose integrated circuits such as microprocessors or random-access memories (RAM) in a computer, an ASIC is implemented for a particular application such as automotive, mobile, medical, home automation, industrial, IoT, and others. Complex versions of an ASIC that include multiple functions, such as microprocessors, peripheral functions, and interfaces, result in a System-on-a-Chip (SoC).
One of the most important aspects of developing a custom ASIC system is differentiating your product from your competitors. Figure 1 is a block diagram showing many of the typical functions that can be included in an ASIC as an SoC design.
Figure 1: Example SoC Block Diagram
You can see in the diagram that many of the functional blocks that are used in a typical ASIC/SoC are either standardized or highly commoditized. There are several benefits to utilizing commercially available IP blocks for these functions, but no real opportunity for differentiation from competitors’ offerings. In fact, for blocks that are completely standards-driven (e.g. the USB interface), it is nearly impossible for there to be any differentiation.
While many of the blocks in an ASIC or SoC are primarily digital in nature, one way to provide market differentiation is to integrate various analog blocks. This has been a trend for over 20 years and will continue to be one for years to come.
History of Analog Integration
The wafer-fab processes and CAD tools used to design and develop ASICs and SoCs tend to be optimized for logic since most of the functions on a typical system are logic. Most systems, however, require several supporting analog functions. Historically, most of those analog functions were supplied by separate, discrete, catalog ICs. The drawbacks of this approach include:
- Larger packages and pin counts
- Additional printed circuit board (PCB) area
- Higher total system cost
- Lack of optimization or differentiation of the catalog analog functions
- Additional implementation complexity
Most ASIC/SoC designs today are implemented in small-geometry processes (40 nm and smaller) to take advantage of both power and die area savings. There are significant challenges to analog circuit design in these small process linewidths, however, due to transistor mismatch and leakage. Despite the many design challenges, some companies, like Vidatronic, design analog functions in the small logic fabrication processes and offer them as Intellectual Property (IP) licenses for integration on-die into larger systems.
As shown in Figure 2, this trend began with Serializer/De-serializer (SERDES) circuits. In the 1990s, most SoCs had wide parallel busses for external I/O that interfaced with external SERDES chips to provide the high-speed serial interfaces. Several different companies worked to overcome the challenges of analog circuit design in non-optimal processes. Today, anytime a high-speed serial interface is required, the IP is available from multiple vendors for nearly every fab and process node. It is now the norm to simply license a SERDES IP and integrate it on-die.
Figure 2: SERDES Integration Trend
Figure 3: Power Management Integration Trend
Figure 3 shows how this trend continues with other analog functions, the latest being on-die power management.
On-Die Power Management
Due to their complex design, SoCs require multiple different power supply rails providing different voltages and currents that can be powered up and down separately under careful control.
Typical functions used in power management include low dropout (LDO) linear voltage regulators, DC-DC converters, voltage references, and security functions. These functions are commonly combined into a dedicated power management unit (PMU) that supplies all of the sub-blocks. The power management blocks, in the left portion of Figure 4 below, are analog and mixed-signal circuits specialized for the application. Each of these blocks can be optimized for a given application resulting in a remarkable improvement in power and price.
Figure 4: Example SoC Block Diagram with Integrated Power Management
To learn more, download our full-length white paper “Analog and Power Management Trends in ASIC and SoC Design.“
- VAD0010SG022 Vidatronic
10-Bit SAR ADC IP for SoC Integration and Hardware Security – 22 nm, supports both ADC/DAC modes
VLDS0500LG022 VidatronicPower Quencher Capless LDO for SoC Integration and Hardware Security – 22 nm, 500 mA, low quiescent current
VBKS0140T040 VidatronicBuck DC-DC Converter for Integrated PMU (Silicon-proven 40 nm, 140 mA, optimized clocking to eliminate spurious emissions