Semiconductor IP News and Trends Blog
ARM Goes Big and Little at the Same Time
Semiconductor IP developers will want to pay close attention to the company’s new “big.LITTLE Processing” paradigm for future integration issues.
Earlier this week, ARM and TSMC announced the tape out of the first 20nm ARM Cortex-A15 core processor. Both companies used Cadence’s RTL-to-sign-off design flow to develop the 20nm test chip.
On the surface, this looks as yet another press release confirming the collaborative roadmap established by the major IP, foundry and EDA providers in the semiconductor business. Why should we care?
The day after this press release was issued, ARM issued a second announcement proclaiming its most energy efficient application processor, the Cortex A7. Aside from a very low power footprint – targeted at the sub-$100 smart phone market – the key element in this release was the discussion of the “big.LITTLE Processing” paradigm.
What does this paradigm have to do with the earlier ARM, TSMC and Cadence tape out?
The A7 will use the big.LITTLE Processing strategy to optimize trade-offs between high performance and low power by pairing the high-performance of the A15 with the low power of the A7. As the ‘LITTLE’, lowest-power processor, the A7 will run the Operating System (OS) and basic Internet applications such as social media and audio playback. As needed, the OS and apps can be migrated to the ‘big,’ higher-performance A-15 processor for tasks such as navigation and gaming. The company claims that the time for this migration is in the order of 20 microseconds.
The trick to such processor pairings has always been in the speed and efficiency with which the two processors partition and share tasks. In the press release, ARM states that; “Big.LITTLE processing allows devices to seamlessly select the right processor for the right task, based on performance requirements.”
Does this approach sound familiar? Intel has been promoting the same paradigm since it reentered the embedded system business in earnest several years ago. The difference seems to be that ARM is promoting both processors in one SoC, whereas Intel has been pairing its low-power Atom processor with a high-performance Xeon chip that typically resides on a server outside the embedded device.
In either case, there are two determinants to success. First, do the two processors truly form a “seamless” unit? In the press release, ARM states the selection of the right processor with the right task will be “transparent to the application software or middleware running on the processors.” This will be critical, since Intel already claims such seamless software development integration with its x86 architectures.
Secondly, how will the two processors interfaced together and within the rest of the SoC – via the AMBA structure? The answer to this question will affect how well existing and new system-level IP interfaces with the processors.
If ARM can meet both of these challenges, then their “big.LITTLE Processing paradigm might be a worthy challenger to Intel’s similar x86-based approach. Undoubtedly, more information will be provided at next week’s ARM TechCon 2011 . (Kudos to ARM’s marketing team on the timing of these two announcements.)