Semiconductor IP News and Trends Blog
Accellera PSS Tutorials – Frequently Asked Questions
The world-wide interest in PSS is growing. We have just finished delivering successful tutorials on behalf of Accellera in Munich (DVcon Europe) and Bangalore (Accellera day). Both events were well-organized and involved multiple interesting topics. The PSS sessions enjoyed packed audience and triggered many good questions from the attendees. For the benefit of those who could not attend, here are the most frequently asked questions and answers from these events.
Question #1: What is the relation between PSS and coverage maximization?
- Some coverage maximization can be achieved on top of UVM and has nothing to do with PSS. For sure, input coverage maximization can be done on top of e/SV languages (e.g. UVM simulators can systematically generate all packet or configuration types).
- But PSS provides powerful semantic that can further enhance maximization by:
- UVM testbench implementation may have many attributes that are not your main project careabouts (e.g. protocol checking related). PSS allows you to isolate properties that you want to focus on, within a concise model, which makes the maximization practical to automate
- PSS main flow is about capturing the legal scenario space within a declarative set of rules. This allows tools to analyze the coverage goals and create scenarios to legally hit un-sampled values.
- PSS allows resource-aware and configuration-aware schedule randomization. For example, if concurrent execution is needed to hit a coverage goal, PSS can devise such a scenario, that would require manual coding of a virtual sequence in UVM.
- Unlike UVM, which generates multiple classes at run-time, PSS allows you to express dependencies between classes and randomize higher level intent upfront. This means that the user can review much of the achieved coverage before running simulations or committing to a long regression.
- Formal capture of the legal scenario space can potentially allow tool to automatically create the coverage ignore directives.
- It is important to understand that PSS is a framework for users to model behavioral dependencies and calls for technology that can analyze and leverage it. Using PSS features in SV/C++ procedural style will block achieving the standard intended value. We highly recommend reading through the PSS LRM introduction and the Accellera tutorials for the proper PSS modeling.
Question #2: Why was coverage added to PSS? Isn’t it the same as SV coverage?
- PSS provides functional coverage capabilities in DSL and C++ to capture verification goals. A full coverage language lets you capture and refine goals to track progress, and steer randomization as needed.
- While the constructs look similar to SV coverage
- PSS coverage lets you capture abstract use-cases that are impractical in SV coverage. For example, try to imagine the model implementation of this scenario in SV: Receive a video from the USB, copy it multiple times to different memory locations, and upload It via the modem.
- PSS coverage is valid for multiple platforms, both gen-time and run-time.
- The combination of the legal scenario space and coverage enables a powerful solution.
Question #3: How do I achieve self-checking in PSS?
- PSS constraints express properties that are checked throughout the execution of scenarios. The improved expressiveness of these constraints in terms of resources and ordering provides a powerful and useful mechanism
- PSS does not have checking features but enables innovative powerful self-checking.
- Self-checking can be achieved in PSS using the following schemes:
- In complex designs where a reference models are too hard to maintain the PSS model can serve as a reference model. Using PSS objects, users can propagate the expected result throughout the action chain and predict the expected value at the end of the scenario or in intermediate points in the middle. If needed, a PSS tool can also activate multiple reference models before, during or post simulation to determine the expected result of a compound scenario.
- Note that since actions can be implemented in either HW or SW, PSS allows creating HW/SW assertions. For example, you can write assertion that if a certain SW activity is performed, N amount of HW snoops should be observed.
Question #4: Can I call SV functions and UVM sequences from PSS?
- PSS can activate any testbench on any execution platform, and as such it allows leveraging UVM assets by calling transactors or activating UVM sequences.
- If portability is a concern it is important to make sure that your reusable scenarios are not locking you into UVM which will make them too slow for Acceleration and not-reusable at other integration levels.
- Having the PSS constraint solver dependent on the SV solver can hold the same concern – it locks the PSS solution to a single HW verification platform and would make a partial model when trying to move to the next integration level. The PSS model should randomize a complete solution that might be targeted to UVM TB as well as non UVM TB.
Questions #5: Can you guys give a PSS demo now?
Answer: Yes. We and other vendors would love to give you a demo of proper PSS modeling, and the expected value. We cannot do it on Accellera stage but would love to demonstrate PSS capabilities right after.
Question #6: What are the differences between UVM virtual sequences and PSS scenarios
- UVM virtual sequences are the way to capture multi-channel scenarios and timing for HW verification.
- The main difference is that solving is much more powerful in PSS. The entire scenario is solved as a single constrained problem, end-to-end and across concurrent/alternative branches. This way, dependencies and restrictions across multiple interacting elements can be accommodated.
- PSS scenarios have the following benefits
- PSS scenarios are automated – While within virtual sequences the user specifies the desired timing and ordering in a directed way (e.g. first do the register configuration and later send the traffic), the PSS tool can leverage the flow objects to automated or auto-complete a partially specified scenario. Both the involved actions and timing are randomized to achieve unexpected or hard-to-achieve scenarios.
- PSS scenarios are integration independent – virtual sequences are typically written for specific integration, they activate specific interface by instance and lock users to a specific VIP implementation. PSS scenarios can auto-adjust to a changing number of interfaces, specific VIP implementation and even to the fact that specific logic can be executed by VIP or a piece of the DUT.
- PSS scenarios can be executed on all platforms. The same randomized behaviors, timing, and intent can be executed:
- Transactional coreless TB or on top of a SW-driven setup
- Pre-silicon or post-silicon platforms
Question #7: Did Accellera choose the UML graphical notations to become official part of the PSS standard.
- PSS is borrowing its core concepts, terms, and semantics from UML: activities, actions, control and data flow between actions, constraints.
- Graphical visualization of scenarios enables productivity
- The ability to visualize scenarios in activity diagrams even before the execution is key to understanding a complex scenario and an enabler for a team’s communication
- Users can create scenarios graphically without learning the PSS syntax, or explore the model legal scenario space interactively, with a UML GUI.
- User can debug scenarios in abstract level and drill into implementation details if needed.
- While Cadence suggested this early on, it is not on the roadmap of the PSWG to officially accept UML activity diagrams graphical notations as part of the standard.
- As can be seen in the PSS LRM and Accellera tutorials, once the standard concepts were agreed upon, contributors converged on such notations that naturally represent flow objects, control flow and loops, ordering and execution flow.
Question #8: Can PSS be adopted now? Should we adopt it ASAP or later?
Answer: Adopting PSS now has multiple benefits.
– If you jump on the standardization bandwagon earlier
- Your current investments would more easily be leveraged in the future
- You would ensure the standard addresses all you need from it
- With SystemVerilog, it took years till enough of the standard was supported on multiple vendor simulators.
- With PSS, a few vendors already announced support and there seems to be an assumption of a shorter support process.
- Using the standard early provides several immediate benefits:
- Enjoy existing automation earlier
- Be safe with industry and multi-vendor support vs. proprietary solution
- Enjoy future automation and innovations that follow a standard introduction.
- As was mentioned before, a PSS tool can provide a lot of value once the user captures the rules of the legal scenario space.
- To enjoy this, make sure the PSS tool you choose and the PSS model you develop both take advantage of the PSS concepts of the full standard promised value.
- Do not settle for a non-standard implementation that would compromise your future.