Semiconductor IP News and Trends Blog

Are Semiconductor Fabs and EDA-IP Ready for FD-SOI?

Recent announcements by the semiconductor foundry and chip design tool industries confirm the growing viability of Silicon-on-Insulator technology.

The recent announcement that Samsung Electronics would source SOI manufacturing is welcome news to the chip community. But does this additional manufacturing capability mean that EDA and IP tool vendors will give greater support to the SoI technology, as Peter Clark suggests in a recent article? Does the gain of the Samsung foundry suggest a loss of support from the GLOBALFOUNDRIES? Let’s focus on the first question.

Shortly after the announcement that STMicroelectronics and Samsung Electronics signed the agreement for multi-sourcing of SOI manufacturing, EDA/IP tool vendor Cadence announced the immediate availability of two intellectual property (IP) solutions for third-party designs on the 28nm FD-SOI process node. (Pay attention to the nodes. I’ll explain why in the next few paragraphs.)

Cadence’s two offerings are in the DDR4 memory and USB interface IP segments. Further, the company announced the qualification of its digital implementation, sign-off and custom/analog design tools for the 28nm FD-SOI process. In the past, the other two major EDA-IP tool vendors have also voiced their support for the FD-SOI ecosystem.

That news looks promising from the EDA/IP side of the chip development equation. But what’s going on with Globalfoundries, a long time supporter of SOI technology. GLOBALFOUNDRIES joined the FD-SOI party almost 2 years ago at the 28nm and 20nm nodes, reports Ed Korczynski, Sr. Technical Editor at SST/SemiMD. “However, though the name has since changed from “20nm” to “14nm” (see table below), work continues nonetheless with GLOBALFOUNDRIES on 14nm FD-SOI with prototyping and IP validation vehicles planned to run by the end of this year. Samsung has so far only licensed the 28nm node technology from ST. A representative of GLOBALFOUNDRIES reached for comment on this news expressed welcome to Samsung as an additional supplier in the FD-SOI ecosystem.”

With the manufacturing cost challenges faced by traditional bulk CMOS HKMG chips at 28nm and below, the transition to a complementary FD-SOI process couldn’t come soon enough. This should mean continued improvement of SOI flow integration into traditional CMOS EDA-IP tool suites.

References:

• SEMICON West 2013: Paul Boudre of Soitec – Soitec’s COO Paul Boudre talks about the competitiveness of full-depleted planar with full-depleted finfet; capacity issues for SOI in light of ST’s open foundry model; and growth of High Resistivity SOI in the RF implementation on smart phones.
• SOI Parity with CMOS Good News for IP Designers – Soitec panel at Semicon West challenges both the IDM model and the dominance of bulk CMOS as material of choice for chips at 20 nm process nodes.
• Mixed-Signal and RF Help Drive Silicon-on-Insulator Growth – Here’s another example of the growing importance of analog/mixed-signal, RF-wireless, and silicon-on-insulator technologies.