Semiconductor IP News and Trends Blog

Automotive Designers Question IP Model Access and Security

A quick curation of past interviews highlights model creation, open system IP, reproducible designs, iTunes EDA, and security approaches from industry experts.

Last week, I spoke to the Seattle chapters of both the Society of Automotive Engineers (SAE) and International Council on System Engineering (INCOSE). The presentation gave an overview of hardware and software integration and co-verification at the chip, board, and vehicle network domain. The best way to verify and integrate at each domain was through the use of model-driven-design (MDD) techniques.

At the end of the presentation, two questions were asked:

1. How secure where these models – especially in light of global development challenges?
2. How available were the hardware and software models? For example, if an automotive developer wanted to run software simulations on ARM or Intel hardware, how would he or she acquire these models? How would different models be connected?

These were great questions! To address them, I pulled from past interviews, articles, and videos. What is listed below is the best of that curation. –JB

I. Security

DAC Panel Explores IP Theft in Global Markets – Here are the essential opening remarks from the DAC Pavilion presentation on the development and integration of IP, delivered by Chipestimate’s General Manager, Adam Traidman. In Part II, noted panelists from GlobalFoundries, IDT, and the legal community will explore the technical, business, and legal challenges of cross-regional IP sourcing and associated worldwide business-integrity challenges.

Security Plays Key Role in IP-based Design Growth – What can be done to reduce the success of reverse-engineering and cloning techniques? One of the best ways to protect any data – be it related to application-software or hardware-design IP – is through the use of sophisticated encryption techniques.

IP Smoke Testing, PSI5 Sensors, and Security Tagging – The thing that has been missing (from IP security) is what to do about soft IP. (Editor’s Note: Soft IP is synthesizable in a high-level language like RTL, C++, Verilog, or VHDL.) “Watermarking the code is a common approach for tracking soft IP and one that we use at IP Extreme. I’ve been working with Kathy Werner, who heads a committee on soft-IP tagging. She has worked with IP at Freescale and then Accellera. Her committee is incorporating many of the same conventions into soft IP that proved successful in hard IP. The goal is that these soft-IP security mechanisms will work throughout the EDA-tool design flow to be propagated downward into the GDSII. In other words, the high-level soft-IP tags could be detected at the GDS level.” – Warren Savage, President & CEO of IP-Extreme

II. Models and Modeling

IP Characterization Moves from The Backroom – “People are getting IP from multiple sources. This presents many challenges – chief of which is how the IP models were created. Since there are no standards for IP model creation, designers use many ad-hoc methods and tools that don’t do a complete job.” – Jim McCanny, CEO of Altos Design Automation

Free Hardware and Software but not IP – “For the silicon industry, there is a tension here, because this industry deals with extremely high-value intellectual property (IP). The silicon design itself represents the “crown jewels” for a silicon company. These designs are traded between companies for large sums under relatively complex licensing terms. Thus, for this industry, the concept of “free” or “open” IP is not easy to mix with their own high-value IP.” – Mark Burton, Founder of the open-source SystemC community and initiative called GreenSoCs

Mysteries of Reproducible Chip Design – “Let’s examine a more controversial and global viewpoint. Imagine a world in which IC design houses described their proudest creations in public documents that told the world every detail. Any reader could download the GDSII file, complete netlist, Verilog source, block diagrams, and every parameter needed to recreate the chip being described. Sounds far-fetched, doesn’t it? This might seem ridiculous in 2007. But consider the world of computers and software 25 years ago…” – Dr. Gary Ray

iTunes Business Model for EDA IP – How do third-party IP vendors in the ASIC and embedded spaces compete with the “free” IP provided by FPGA companies? System-Level Design explored this question with OptNgn Software, a startup company.