Semiconductor IP News and Trends Blog
Chip Design Enters the Third Dimension
How will stacked die affect the IP supply chain? FinFet transistor structures will require new Spice models. But what else?
Today is a mix of medias – all dealing with the coming die and chip 3D challenges:
1. My colleague and editor-in-chief of the Low-Power High-Performance portal – Ed Sperling – has written a three-part IP-supply-chain series based upon interviews with the following: Jim Hogan, an independent VC; Jack Brown, senior vice president at Sonics; Mike Gianfagna, vice president of marketing at Atrenta; Paul Hollingworth, vice president of strategic accounts at eSilicon, and Warren Savage, CEO of IPextreme. Here’s the last of that series: Experts At The Table: The Business Of IP
– Notable quote from Warren Savage, CEO of IPextreme, responding to a question about the future of IP on stacked die:
2. In this short video, Sean O’Kane from Chipestimate.TV and I talk with ARM’s John Heinlein about the coming challenges faced by IP designers using FinFet transistor structures.
– TSMC OIP 2012 – John Heinlein interview