Semiconductor IP News and Trends Blog
DAC Panel Explores IP Theft in Global Markets
Here are the essential opening remarks from the DAC Pavilion presentation on the development and integration of IP, delivered by Chipestimate’s General Manager, Adam Traidman. In Part II, noted panelists from GlobalFoundries, IDT and the legal community will explore the technical, business, and legal challenges of cross-regional IP sourcing and associated worldwide business integrity challenges.
Analysts at Gartner-Dataquest predict that the combined market for design and verification semiconductor IP will be just under $2 billion by 2011. This market has been growing fast. Our own aggregated chip estimation data – from the Chipestimate.com database – combined with other sources reveals another interesting data point. A decade ago, 19 percent of the chip die area consisted of IP reused from a prior design generation or from multiple chips. Last year, that same die area rose to 78 percent of the chip. This change represents a huge acceleration in the reuse of IP.
We are seeing evidence of this reuse across all sizes of semiconductor companies. In small companies, limited engineering resources make IP reuse value proposition more attractive. For example, instead of designing a required interface for which there is no internal engineering talent, a small company could secure that interface IP from a trusted, quality supplier. Buying this IP would typically be cheaper and take less time than if the startup designed and built the IP themself. Such a value proposition makes sense.
But even large companies, such as Intel and IBM, are accelerating their use of IP. To understand why this acceleration is taking place, we need to look at the beginnings of the EDA industry.
Twenty or so years ago, EDA companies like Cadence and Synopsys were forming. These early companies were essentially competing with the internal EDA- and CAD-based tool organizations of large semiconductor companies. Ultimately, these large companies outsourced the creation, development and maintenance of these tools,which helped create the EDA industry – everything that we see around us today hear at the Design Automation Conference (DAC).
We are now seeing that same trend in the area of IP. Consider interface IP, where you can check that the interface conforms to a specification. This gives you the confidence that it will meet your needs. We are seeing a lot of divestment of that internal IP creation for those standard interfaces and related STAR IPs, like processors, memories and the like. There is also a lot more sourcing. All of these activities suggest that the IP industry is mature to a point where suppliers are trusted to generate a good quality product. Also, EDA companies and designer have the tools and methodologies that they need to do a good job of integrating and verifying that IP.
This sets the content for the growth and evolution of today’s semiconductor IP industry, as well as why IP reuse is the de-facto model for SOC development. Emerging markets are increasingly becoming both consumers and suppliers of design IP. But this growth raises many questions. What about the technical, business, and legal aspects of cross-regional IP sourcing? What can the IP ecosystem do to promote business integrity worldwide?
Experts from Globalfoundries, IDT and the legal community – all involved in the development and integration of IP – address those question in Part II (next blog). Stay tuned!