Semiconductor IP News and Trends Blog

DVCon Keynote: Future of Verification lies in Portable Test Benches

For Mentor’s CEO Wally Rhines, the future of IP and chip design lies in verification engine abstraction as highlighted by Accellera’s reusable test bench pre-standard.

By John Blyler, Editorial Director

Mentor Graphic’s CEO Wally Rhines delivered the DVCon 2016 keynote in which he focused on chip design and verification challenges from the past, present and into the future. Others have covered the past and present challenges in optimizing individual verification engines. I’ll focus on the future where Rhines envisioned significant productivity improvements by bringing together all of these individual engines from virtual prototypes, formal verification, simulation, emulation to FPGA prototyping.

Today’s chip verification process needs to be abstracted from the underline verification engines. This is known as separating the “what” from the “how,” where the design-verification engineer determines the “what” while the tools generate the “how.” Rhines illustrated this point with a quote from Intel’s principal engineer Bill Hodges: “Users should not be able to tell if their job was executed on a simulator, an emulator or a prototype.”

Accellera, the chip design, modeling, and verification standards body, is currently supporting this abstraction by trying to create portable test benches. Stimulus for these test benches would run on different target engines – for example, simulator, emulator, and FPGA prototypes. Such stimulus would also be portable and reusable throughout the design process, from the intellectual property (IP) blocks to the higher level subsystem and full system test. Stimulus that is portable across many chip design and verification engines would have a major positive impact on overall productivity.

“The problem is that people have different needs which lead to different source languages for verification,” Rhines explained.  For example, chip architects typically work with SystemC, whereas software developers use C/C++. Verification engineers prefer System Verilog and software test and validation engineers use C/C++. All of these different source languages must come together to create a compatible and portable test bench.

Shishpal Rawat, Accellera Systems Initiative Chair, put it this way: “Can we create a language that allows us to write once but use many times in these environments as we step through the various phases of simulation and the design?”

The specification language would have generators to deal with different environments like System Verilog, gate level analysis, test and so on, noted Rawat.  The Initial scope for the Accellera Portable Stimulus Working Group (PSWG) is to define a portable test and stimulus specification language that can be used to generate stimulus for multiple target implementations.

The final goal is to have a single declarative input specification to enable the test creation automation, noted Rhines. Such a specification will enable the automatic generation of tests – that is, the “hows.” Further, tools will generate these tests that can then be reused across all of the various platforms.