Semiconductor IP News and Trends Blog
DVCon U.S. Serves Chip Users Latest Tools and Standards
The Design and Verification Conference and Exhibition (DVCon U.S.) held earlier this year once again brought chip developers together with EDA tool vendors to tackle major issues.
By John Blyler, Editor, IP Insider
To practicing chip design and verification engineers, DVCon remains one of the few events that really connects end users and EDA tool vendors. It is neither a purely academic- nor exhibitor-centric event, but rather a tool-agnostic technical user conference.
This year’s DVCon U.S. General Chair, Aparna Dey, put it this way: “We are very proud that our technical programs, tutorials, short workshops and panels not only covered key verification topics, but also included a number of new topics that attracted standing-room-only attendance. Our exhibition was a major draw for both attendees and exhibitors and was a gathering place for DV (design-verification) engineers and their peers to discuss the latest in technology and design.”
In addition to technically rich content, DVCon U.S. 2019 hosted the annual awards for best presentations. This year, the Best Paper Award was posthumously named the Stuart Sutherland Best Paper Award. The name change honored Stu’s expertise in Verilog and SystemVerilog, his past position as General Chair of DVCon U.S. and year’s of service on the Technical Program Committee (TPC).
As voted by conference attendees, the Stuart Sutherland Best Paper Award went to Cliff Cummings, Sunburst Design, Inc. (see Figure 1), and John Rose and Adam Sherer, Cadence Design Systems for their presentation, “Yikes! Why Is My SystemVerilog Still So Slooooow?” Second place was awarded to Horace Chan and Byron Watt, Microchip Technology, Inc. for their presentation, “How to Test the Whole Firmware/Software when the RTL Can’t Fit the Emulator,” and third place was awarded to Ang Li, Hao Chen, Jason Yu, EeLoon Teoh, and Iswerya Prem Anand, Intel Corp. for their paper, “A Coverage-Driven Formal Methodology for Verification Sign-off.”
An important component of DVCon conferences is the close connection with the chip design and verification standards body known as the Accellera Systems Initiative (or just “Accellera”). One of the latest Accellera working groups – “IP Security Assurance (IP SA) – held a face-to-face meeting during this expo. DVCon often serves as a place where such standards related meetings take place and where new members attending the expo might also join.
Several existing standards were featured in short workshops, tutorials and presentations including SystemC, UVM and Portable Stimulus. Updates and new implementation approaches are constantly being worked upon within existing standards. This is why Accellera continually engages in close collaboration with the IEEE Computer Society’s Design Automation Standards Committee (DASC) (see Figure 2). (See, “A Unique Collaboration: Revitalizing Existing Standards While Preparing for the Future”)
Other highlights from DVCon U.S. 2019 included:
- Tom Fitzpatrick received the 2019 Accellera Technical Excellence Award for his outstanding contributions to UVM and Portable Stimulus
- Fram Akiki, vice president, Electronics & Semiconductor Industry for Siemens PLM Software, provided the keynote focusing on digital transformation. Broadening the scope beyond Electronic Design Automation, he highlighted IC verification as an important foundation for extending the digital twin into important applications such as autonomous driving and intelligent, connected devices.
- Several noteworthy panels occurred during the conference. The first panel, “Verification and Compliance in the Era of Open ISA – Is the Industry Ready to Address the Coming Tsunami of Innovation?” explored the hot topic of the RISC-V instruction set architecture, its features and benefits as well as the challenges for processor IP and SoC development and verification. The second panel, “Deep Learning –– Reshaping the Verification Landscape or Business as Usual?” had a packed ballroom of attendees learning about the next steps for AI and machine learning and how they will reshape the semiconductor industry.
DVCon has truly become a global event with conferences and exhibitions occurring in the US, Europe, China and India. Each DVCon has a similar “look and feel” with a focus on user contribution and papers written by and presented by the users, not just papers about product paid by sponsors. Yet each one is tailored to the specific region and country. For example, DVCon Europe recently included a SystemC-focused day co-located with the conference. Meanwhile, DVCon China is newer and still in start-up mode but should expand to a fuller two-day event next year, observed Lu Dai, Accellera Chair.
“DVCon global membership covers over 11 countries,” explained Dai. “One of the ways that we grow our user communities is through public forums where users can ask technical questions of the working group members. For example, in Europe, one popular forum deals with SystemC. In the US, the portable stimulus forum has gained a lot of attention by the user community.”
There are similar forums in both India and China. Regardless of the country, DVCon strives to engage the technical chip user and tool vendor communities as well as aid Accellera in the development of world-class standards.
If you’d like to contribute to DVCon U.S. 2020, the call for contributions is now available. The deadline for extended abstracts is August 12 and the deadline for short workshop, panel and tutorial proposals is September 24.