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About the Author

Sangeeta is responsible for deployment of PCIe and CXL VIP product line for Cadence Design Systems. Sangeeta has 10+ years of experience in VIP development and deployment. Over the years, she has collaborated with multiple key industry driving clients. She has vast experience of working on IP, Subsystem and SoC level including PCIe, CXL and PHY DUTs. She holds BTech degree in Electronics and Communication.

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