Semiconductor IP News and Trends Blog

EDA Giants Place in IP Survey

Surveys present conflicting evidence on semiconductor intellectual property (IP) position key EDA vendors Cadence and Synopsys.

By John Blyler, Editorial Director, Semi-IP Systems

Meaningful surveys in the EDA realm of intellectual property (IP) are hard to come by. Thus any bit of news can be useful. The results of John Cooley’s 2014 “Rorschach Test” IP survey and ARM’s pre-SoftBank acquisition announcement presented me with a good opportunity to comment about EDA chip-design tool IP. In Cooley’s survey, ARM’s ranks expectedly high while Cadence ranks unexpectedly low in IP offerings.

Before I go on and in all fairness to Cooley, his survey was very impromptu. He explained that the survey, when responded to by the DeepChip subscribers, had “accidentally morphed into an overall glimpse of what IP chip designers and verification engineers were using worldwide.” Cooley recognized that this particular survey was not statistically reliable, which is why he humorously called it a Rorschach test rather than an official survey. Fair enough.

My interest in surveys stem from long experience conducting the Chip Design Trends (CDT) technical/market surveys. What follows is my rough comparison of Cooley’s 2014 “Rorschach Test” survey with portions of two surveys from my 2012-2013 Chip Design Trends (CDT) surveys: “EDA Tools” and “ASIC Prototyping with FPGAs. Note that each survey received relatively the same number of respondents (~150) although the type of respondents to Cooley’s Rorschach Test is unknown. The CDT participants consisted of SOC developers who had actively worked on designs within the last 2 1/2 years.

My somewhat boring conclusion is that Synopsys and Cadence rank high in IP technology. But the less boring evidence reveals that other issues are of more concern in chip development but IP concerns outweigh those of software developers in the chip space. What follows are my comparisons of these two surveys. — JB

I. John Cooley’s IP Survey:

Cooley’s Survey – Question #2: What type of IP (hard/soft/VIP) INTERESTED you this year? For what specific protocols/uPs/memories/standards? What company made the IP you’re interested in?”

ARM and SYNOPSYS KICK ASS: If you tabulate how many times what each engineer had said about a specific IP/VIP vendor, it breaks out to:

something ARM: ##################################### 37%
something Synopsys: ################################### 35%
something Mentor: ########## 10%
something ImgTec MIPS: #### 4%
something SNPS ARC: #### 4%
something Sonics: #### 4%
something CEVA: #### 4%
something Cadence: #### 4%
something Arasan: ### 3%

II. Chip Design Trends:

EDA Survey – Q14: If (developing) an SoC, do you use third party IP? If so, what

Answer (see Figure 1): Not surprisingly, the largest usage of third party IP was for digital logic, embedded processors, and memory, followed more distantly by mixed signal, RF-Wireless and IO. This roughly corresponds to Cooley’s survey where ARM, Synopsys (memory and ARC processor) and Mentor (Ethernet, USB, sans Tanner AMS) play the major role. Why Cadence (with Denali memory and IO) doesn’t play a major role in his survey is unknown.

Figure 1: Third Party IP. Courtesy of Chip Design Trends (CDT).

EDA Survey – Q47: In what areas of design are the EDA companies as an industry the weakest?

Answer (see Figure 2): Verification IP garnished only 16.7% while semiconductor IP (availability) was at 5.6%. Leading was yield management (44.5%), testing (DFT, ATPG) at 33.3% and tied at third were Circuit Simulation (i.e. AMS, RF), Virtual Prototyping and High-Level Synthesis at 27.8%. This is not really a fair comparison in that Cooley’s survey only asked about IP. But one should note that Synopsys, Cadence and Mentor all have major tool suits in most of these areas.

Figure 2: Design Areas

ASIC Proto Survey – Q49L: FPGA prototyping: If you are using or are planning to use FPGA based prototyping, please describe the use mode.

Answer: In 2012, hardware-software co-design and co-verification were again the number one reason for ASIC designers to use FPGA-based prototypes (see Figure 3). Not surprisingly, hardware chip verification was the second leading driver, followed by software and then system verification.

A surprise comes when designers were asked about future planned projects. All of the above current motivators are still there, but respondents indicated that software development would fall behind IP development and verification as an important issue. This probably means that IP development and verification has proved to be a sore spot for today’s designers.

This seems to support Cooley’s focus on the IP question in his survey.

Figure 3: Current and planned reasons why ASIC/ASSP chip designers use FPGA-based prototypes.

Overall Conclusions:

Cooley’s survey ranks Synopsys very in terms of what type of IP is most mentioned by his respondents. Conversely, the Chip Design Trends (CDT) survey from roughly the same time and containing roughly the same number of respondents didn’t rank IP vendors but instead prioritized IP design and verification issues in the process of creating a system-on-chip (SOC). The CDT survey confirms that that the vendors with the best design chain integration with foundries and IP suppliers are both Synopsys and Cadence (see Figure 4).

There is no evidence that Cadence is a minor player in IP as suggested by the Cooley survey.

What remains interesting to me is that IP issues fall behind simulation/virtual prototyping/high-level synthesis, manufacturing and testing concerns. The other point of interest was that, while software development costs often outpace those of chip design, software falls behind IP development and verification as a critical issues for chip designers. Obviously, a future study could give further insight into these issues.

Figure 4: Best design chain integration.